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Merged
merged 7 commits into from
Apr 26, 2025
Merged

[TTI] Simplify implementation (NFCI) #136674

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c1c933f
Remove TargetTransformInfo::Model
s-barannikov Apr 22, 2025
8e138ef
override everything
s-barannikov Apr 22, 2025
ead188b
Remove TargetTransformInfo::Concept
s-barannikov Apr 22, 2025
7509894
Merge commit 'd20604e5b6792bd010dd4dfd36f3e836ae0fe7b2' into tti/remo…
s-barannikov Apr 23, 2025
ca0a268
Merge branch 'main' into tti/remove-concept-model
s-barannikov Apr 26, 2025
c042732
Update code comments
s-barannikov Apr 26, 2025
3ea8317
Merge branch 'main' into tti/remove-concept-model
s-barannikov Apr 26, 2025
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1,360 changes: 4 additions & 1,356 deletions llvm/include/llvm/Analysis/TargetTransformInfo.h
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728 changes: 399 additions & 329 deletions llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
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293 changes: 153 additions & 140 deletions llvm/include/llvm/CodeGen/BasicTTIImpl.h
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8 changes: 6 additions & 2 deletions llvm/lib/Analysis/TargetTransformInfo.cpp
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Expand Up @@ -57,6 +57,10 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
};
} // namespace

TargetTransformInfo::TargetTransformInfo(
std::unique_ptr<const TargetTransformInfoImplBase> Impl)
: TTIImpl(std::move(Impl)) {}

bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
// If the loop has irreducible control flow, it can not be converted to
// Hardware loop.
Expand Down Expand Up @@ -199,7 +203,7 @@ bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
}

TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
: TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
: TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}

TargetTransformInfo::~TargetTransformInfo() = default;

Expand Down Expand Up @@ -1472,7 +1476,7 @@ void TargetTransformInfo::collectKernelLaunchBounds(
return TTIImpl->collectKernelLaunchBounds(F, LB);
}

TargetTransformInfo::Concept::~Concept() = default;
TargetTransformInfoImplBase::~TargetTransformInfoImplBase() = default;

TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp
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Expand Up @@ -103,7 +103,7 @@ CodeGenTargetMachineImpl::CodeGenTargetMachineImpl(

TargetTransformInfo
CodeGenTargetMachineImpl::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(BasicTTIImpl(this, F));
return TargetTransformInfo(std::make_unique<BasicTTIImpl>(this, F));
}

/// addPassesToX helper drives creation and initialization of TargetPassConfig.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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Expand Up @@ -582,7 +582,7 @@ void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {

TargetTransformInfo
AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(AArch64TTIImpl(this, F));
return TargetTransformInfo(std::make_unique<AArch64TTIImpl>(this, F));
}

TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
Expand Down
236 changes: 124 additions & 112 deletions llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
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Expand Up @@ -1070,7 +1070,7 @@ GCNTargetMachine::getSubtargetImpl(const Function &F) const {

TargetTransformInfo
GCNTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(GCNTTIImpl(this, F));
return TargetTransformInfo(std::make_unique<GCNTTIImpl>(this, F));
}

Error GCNTargetMachine::buildCodeGenPipeline(
Expand Down
125 changes: 65 additions & 60 deletions llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
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Expand Up @@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// This file a TargetTransformInfoImplBase conforming object specific to the
/// AMDGPU target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
Expand Down Expand Up @@ -52,12 +52,12 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE) const;
OptimizationRemarkEmitter *ORE) const override;

void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
TTI::PeelingPreferences &PP) const;
TTI::PeelingPreferences &PP) const override;

uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
};

class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
Expand Down Expand Up @@ -104,64 +104,65 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
public:
explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);

bool hasBranchDivergence(const Function *F = nullptr) const;
bool hasBranchDivergence(const Function *F = nullptr) const override;

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE) const;
OptimizationRemarkEmitter *ORE) const override;

void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
TTI::PeelingPreferences &PP) const;
TTI::PeelingPreferences &PP) const override;

TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const {
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override {
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
return TTI::PSK_FastHardware;
}

unsigned getNumberOfRegisters(unsigned RCID) const;
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
unsigned getMinVectorRegisterBitWidth() const;
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
unsigned getNumberOfRegisters(unsigned RCID) const override;
TypeSize
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
unsigned getMinVectorRegisterBitWidth() const override;
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
unsigned ChainSizeInBytes,
VectorType *VecTy) const;
VectorType *VecTy) const override;
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
unsigned ChainSizeInBytes,
VectorType *VecTy) const;
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
VectorType *VecTy) const override;
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;

bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
unsigned AddrSpace) const override;
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
unsigned AddrSpace) const override;

uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
Type *
getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
unsigned SrcAddrSpace, unsigned DestAddrSpace,
Align SrcAlign, Align DestAlign,
std::optional<uint32_t> AtomicElementSize) const;
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
Type *getMemcpyLoopLoweringType(
LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
std::optional<uint32_t> AtomicElementSize) const override;

void getMemcpyLoopResidualLoweringType(
SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
Align SrcAlign, Align DestAlign,
std::optional<uint32_t> AtomicCpySize) const;
unsigned getMaxInterleaveFactor(ElementCount VF) const;
std::optional<uint32_t> AtomicCpySize) const override;
unsigned getMaxInterleaveFactor(ElementCount VF) const override;

bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
bool getTgtMemIntrinsic(IntrinsicInst *Inst,
MemIntrinsicInfo &Info) const override;

InstructionCost getArithmeticInstrCost(
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
ArrayRef<const Value *> Args = {},
const Instruction *CxtI = nullptr) const;
const Instruction *CxtI = nullptr) const override;

InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) const;
const Instruction *I = nullptr) const override;

bool isInlineAsmSourceOfDivergence(const CallInst *CI,
ArrayRef<unsigned> Indices = {}) const;
Expand All @@ -170,13 +171,13 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
TTI::TargetCostKind CostKind,
unsigned Index, Value *Op0,
Value *Op1) const;
Value *Op1) const override;

bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const;
bool isSourceOfDivergence(const Value *V) const;
bool isAlwaysUniform(const Value *V) const;
bool isSourceOfDivergence(const Value *V) const override;
bool isAlwaysUniform(const Value *V) const override;

bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
// Address space casts must cast between different address spaces.
if (FromAS == ToAS)
return false;
Expand All @@ -197,11 +198,11 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
return false;
}

bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override {
return AMDGPU::addrspacesMayAlias(AS0, AS1);
}

unsigned getFlatAddressSpace() const {
unsigned getFlatAddressSpace() const override {
// Don't bother running InferAddressSpaces pass on graphics shaders which
// don't use flat addressing.
if (IsGraphics)
Expand All @@ -210,24 +211,25 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
}

bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
Intrinsic::ID IID) const;
Intrinsic::ID IID) const override;

bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const {
bool
canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
AS != AMDGPUAS::PRIVATE_ADDRESS;
}

Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
Value *NewV) const;
Value *NewV) const override;

bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0,
const Value *Op1, InstCombiner &IC) const;

bool simplifyDemandedLaneMaskArg(InstCombiner &IC, IntrinsicInst &II,
unsigned LaneAgIdx) const;

std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const;
std::optional<Instruction *>
instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override;

Value *simplifyAMDGCNLaneIntrinsicDemanded(InstCombiner &IC,
IntrinsicInst &II,
Expand All @@ -238,40 +240,43 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
APInt &UndefElts2, APInt &UndefElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const;
SimplifyAndSetOp) const override;

InstructionCost getVectorSplitCost() const { return 0; }

InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index,
VectorType *SubTp,
ArrayRef<const Value *> Args = {},
const Instruction *CxtI = nullptr) const;
InstructionCost
getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
ArrayRef<const Value *> Args = {},
const Instruction *CxtI = nullptr) const override;

bool isProfitableToSinkOperands(Instruction *I,
SmallVectorImpl<Use *> &Ops) const;
SmallVectorImpl<Use *> &Ops) const override;

bool areInlineCompatible(const Function *Caller,
const Function *Callee) const;
const Function *Callee) const override;

int getInliningLastCallToStaticBonus() const;
unsigned getInliningThresholdMultiplier() const { return 11; }
unsigned adjustInliningThreshold(const CallBase *CB) const;
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const;
int getInliningLastCallToStaticBonus() const override;
unsigned getInliningThresholdMultiplier() const override { return 11; }
unsigned adjustInliningThreshold(const CallBase *CB) const override;
unsigned getCallerAllocaCost(const CallBase *CB,
const AllocaInst *AI) const override;

int getInlinerVectorBonusPercent() const { return InlinerVectorBonusPercent; }
int getInlinerVectorBonusPercent() const override {
return InlinerVectorBonusPercent;
}

InstructionCost
getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
std::optional<FastMathFlags> FMF,
TTI::TargetCostKind CostKind) const;
TTI::TargetCostKind CostKind) const override;

InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const;
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
FastMathFlags FMF,
TTI::TargetCostKind CostKind) const;
InstructionCost
getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind) const override;
InstructionCost
getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
TTI::TargetCostKind CostKind) const override;

/// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
unsigned getCacheLineSize() const override { return 128; }
Expand All @@ -284,7 +289,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
bool shouldPrefetchAddressSpace(unsigned AS) const override;
void collectKernelLaunchBounds(
const Function &F,
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const;
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const override;
};

} // end namespace llvm
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
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Expand Up @@ -87,7 +87,7 @@ R600TargetMachine::getSubtargetImpl(const Function &F) const {

TargetTransformInfo
R600TargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(R600TTIImpl(this, F));
return TargetTransformInfo(std::make_unique<R600TTIImpl>(this, F));
}

ScheduleDAGInstrs *
Expand Down
25 changes: 13 additions & 12 deletions llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h
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Expand Up @@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
//
/// \file
/// This file a TargetTransformInfo::Concept conforming object specific to the
/// This file a TargetTransformInfoImplBase conforming object specific to the
/// R600 target machine. It uses the target's detailed information to
/// provide more precise answers to certain TTI queries, while letting the
/// target independent and default TTI implementations handle the rest.
Expand Down Expand Up @@ -43,28 +43,29 @@ class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {

void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
TTI::UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE) const;
OptimizationRemarkEmitter *ORE) const override;
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
TTI::PeelingPreferences &PP) const;
TTI::PeelingPreferences &PP) const override;
unsigned getHardwareNumberOfRegisters(bool Vec) const;
unsigned getNumberOfRegisters(unsigned ClassID) const;
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
unsigned getMinVectorRegisterBitWidth() const;
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
unsigned getNumberOfRegisters(unsigned ClassID) const override;
TypeSize
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
unsigned getMinVectorRegisterBitWidth() const override;
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
unsigned AddrSpace) const override;
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
unsigned AddrSpace) const;
unsigned getMaxInterleaveFactor(ElementCount VF) const;
unsigned AddrSpace) const override;
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
const Instruction *I = nullptr) const;
const Instruction *I = nullptr) const override;
using BaseT::getVectorInstrCost;
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
TTI::TargetCostKind CostKind,
unsigned Index, Value *Op0,
Value *Op1) const;
Value *Op1) const override;
};

} // end namespace llvm
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCTargetMachine.cpp
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Expand Up @@ -103,5 +103,5 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {

TargetTransformInfo
ARCTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(ARCTTIImpl(this, F));
return TargetTransformInfo(std::make_unique<ARCTTIImpl>(this, F));
}
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARC/ARCTargetTransformInfo.h
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Expand Up @@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
// \file
// This file contains a TargetTransformInfo::Concept conforming object specific
// This file contains a TargetTransformInfoImplBase conforming object specific
// to the ARC target machine. It uses the target's detailed information to
// provide more precise answers to certain TTI queries, while letting the
// target independent and default TTI implementations handle the rest.
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMTargetMachine.cpp
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Expand Up @@ -322,7 +322,7 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {

TargetTransformInfo
ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
return TargetTransformInfo(ARMTTIImpl(this, F));
return TargetTransformInfo(std::make_unique<ARMTTIImpl>(this, F));
}

ScheduleDAGInstrs *
Expand Down
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