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[X86][GlobalIsel] support G_FABS #136718

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Merged
merged 16 commits into from
Jun 25, 2025
Merged

[X86][GlobalIsel] support G_FABS #136718

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d4475cb
[X86][GlobalIsel] support fabs for f80
Apr 22, 2025
22e2c83
add float and double
Apr 24, 2025
0ed32a7
update test
May 1, 2025
8221bc6
remove s8
May 1, 2025
6a58699
update fabs for f32 and f64
May 27, 2025
db0e1cb
fix indent
May 27, 2025
f35b674
add x87 specific runs
Jun 3, 2025
2782568
fix tst
Jun 5, 2025
860903d
remove unused marker
Jun 5, 2025
d4d3d44
fix clang format
Jun 7, 2025
4838b22
fix clang format
Jun 7, 2025
63eebe0
remove const pool
Jun 11, 2025
a718a5b
remove noise
Jun 11, 2025
e57ab03
add fallback
Jun 19, 2025
f5e5274
format extension issue
Jun 19, 2025
ac44b20
Merge branch 'main' into gisel_fabs
RKSimon Jun 25, 2025
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33 changes: 33 additions & 0 deletions llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,8 @@ class X86InstructionSelector : public InstructionSelector {
MachineFunction &MF) const;
bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectFAbs(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI) const;
Expand Down Expand Up @@ -391,6 +393,8 @@ bool X86InstructionSelector::select(MachineInstr &I) {
switch (I.getOpcode()) {
default:
return false;
case TargetOpcode::G_FABS:
return selectFAbs(I, MRI, MF);
case TargetOpcode::G_STORE:
case TargetOpcode::G_LOAD:
return selectLoadStoreOp(I, MRI, MF);
Expand Down Expand Up @@ -1050,6 +1054,35 @@ bool X86InstructionSelector::selectCmp(MachineInstr &I,
I.eraseFromParent();
return true;
}
bool X86InstructionSelector::selectFAbs(MachineInstr &I,
MachineRegisterInfo &MRI,
MachineFunction &MF) const {
assert((I.getOpcode() == TargetOpcode::G_FABS) && "unexpected instruction");
Register SrcReg = I.getOperand(1).getReg();
Register DstReg = I.getOperand(0).getReg();
LLT Ty = MRI.getType(SrcReg);
unsigned OpAbs;
const TargetRegisterClass *DstRC;
switch (Ty.getSizeInBits()) {
default:
return false;
case 32:
OpAbs = X86::ABS_Fp32;
DstRC = &X86::FR32RegClass;
break;
case 64:
OpAbs = X86::ABS_Fp64;
DstRC = &X86::FR64RegClass;
break;
}
MRI.setRegClass(DstReg, DstRC);
MachineInstr &FAbsInst =
*BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpAbs), DstReg)
.addReg(SrcReg);
constrainSelectedInstRegOperands(FAbsInst, TII, TRI, RBI);
I.eraseFromParent();
return true;
}

bool X86InstructionSelector::selectFCmp(MachineInstr &I,
MachineRegisterInfo &MRI,
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Expand Up @@ -418,6 +418,10 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.legalFor(HasAVX512, {v16s32, v8s64})
.legalFor(UseX87, {s80});

getActionDefinitionsBuilder(G_FABS)
.legalFor(UseX87 && !HasSSE2 && !HasSSE1, {s64, s80})
.lower();
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Does lower generate the selectable code? Then we probably can add tests for float and double as well.

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+x87,-sse,-sse2 restricts SDAG Isel for float and double. It requires SSE.
exact message SSE register return with SSE disabled.

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that error comes from the globalisel code, not sdag. You can also just stop testing with those features forced off

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We use X87 with and without SSE for s80. So there is no need forcing -sse.

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that error comes from the globalisel code, not sdag. You can also just stop testing with those features forced off
@arsenm It appeared without gisel too.
https://godbolt.org/z/Goc3zs9qe
@e-kud I can drop using -sse 👍


// fp comparison
getActionDefinitionsBuilder(G_FCMP)
.legalFor(HasSSE1 || UseX87, {s8, s32})
Expand Down
46 changes: 43 additions & 3 deletions llvm/test/CodeGen/X86/isel-fabs-x87.ll
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Original file line number Diff line number Diff line change
@@ -1,8 +1,48 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse | FileCheck %s --check-prefixes=X86,SDAG-ISEL
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -fast-isel | FileCheck %s --check-prefixes=X86,Fast-ISEL
; RUN: llc < %s -mtriple=i686-- -mattr=+x87,-sse2,-sse -global-isel -global-isel-abort=0 | FileCheck %s --check-prefixes=X86,GISEL-ISEL

define void @test_float_abs(ptr %argptr) {
; SDAG-ISEL-LABEL: test_float_abs:
; SDAG-ISEL: # %bb.0:
; SDAG-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
; SDAG-ISEL-NEXT: andb $127, 3(%eax)
; SDAG-ISEL-NEXT: retl
;
; Fast-ISEL-LABEL: test_float_abs:
; Fast-ISEL: # %bb.0:
; Fast-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
; Fast-ISEL-NEXT: andb $127, 3(%eax)
; Fast-ISEL-NEXT: retl
;
; GISEL-ISEL-LABEL: test_float_abs:
; GISEL-ISEL: # %bb.0:
; GISEL-ISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
; GISEL-ISEL-NEXT: andl $2147483647, (%eax) # imm = 0x7FFFFFFF
; GISEL-ISEL-NEXT: retl
%arg = load float, float* %argptr
%abs = tail call float @llvm.fabs.f32(float %arg)
store float %abs, ptr %argptr
ret void
}

define void @test_double_abs(ptr %argptr) {
; X86-LABEL: test_double_abs:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: fldl (%eax)
; X86-NEXT: fabs
; X86-NEXT: fstpl (%eax)
; X86-NEXT: retl
%arg = load double, double* %argptr
%abs = tail call double @llvm.fabs.f64(double %arg)
store double %abs, double* %argptr
ret void
}

define x86_fp80 @test_x86_fp80_abs(x86_fp80 %arg) {
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Probably would be nice to see how we handle floats and double without SSE.

; X64-LABEL: test_x86_fp80_abs:
Expand Down
66 changes: 53 additions & 13 deletions llvm/test/CodeGen/X86/isel-fabs.ll
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@@ -1,37 +1,61 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=i686-- -mattr=-x87 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=-x87 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=FASTISEL-X86
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,+sse,+sse2 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,+sse,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64
; RUN: llc < %s -mtriple=x86_64-- -mattr=-x87,+sse,+sse2 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64
; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse,+sse2 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=FASTISEL-X86
; RUN: llc < %s -mtriple=i686-- -mattr=-x87,+sse,+sse2 -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86


define float @test_float_abs(float %arg) {
define float @test_float_abs(float %arg) nounwind {
; X64-LABEL: test_float_abs:
; X64: # %bb.0:
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
; GISEL-X64-LABEL: test_float_abs:
; GISEL-X64: # %bb.0:
; GISEL-X64-NEXT: movd %xmm0, %eax
; GISEL-X64-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; GISEL-X64-NEXT: movd %eax, %xmm0
; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_float_abs:
; X86: # %bb.0:
; X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movd %xmm0, %eax
; X86-NEXT: retl
;
; FASTISEL-X86-LABEL: test_float_abs:
; FASTISEL-X86: # %bb.0:
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: andl $2147483647, %eax # imm = 0x7FFFFFFF
; FASTISEL-X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; FASTISEL-X86-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; FASTISEL-X86-NEXT: movd %xmm0, %eax
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: test_float_abs:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: retl
%abs = tail call float @llvm.fabs.f32(float %arg)
ret float %abs
}

define double @test_double_abs(double %arg) {
define double @test_double_abs(double %arg) nounwind {
; X64-LABEL: test_double_abs:
; X64: # %bb.0:
; X64-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; X64-NEXT: retq
;
; GISEL-X64-LABEL: test_double_abs:
; GISEL-X64: # %bb.0:
; GISEL-X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; GISEL-X64-NEXT: movq %xmm0, %rcx
; GISEL-X64-NEXT: andq %rax, %rcx
; GISEL-X64-NEXT: movq %rcx, %xmm0
; GISEL-X64-NEXT: retq
;
; X86-LABEL: test_double_abs:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -41,10 +65,26 @@ define double @test_double_abs(double %arg) {
;
; FASTISEL-X86-LABEL: test_double_abs:
; FASTISEL-X86: # %bb.0:
; FASTISEL-X86-NEXT: pushl %ebp
; FASTISEL-X86-NEXT: movl %esp, %ebp
; FASTISEL-X86-NEXT: andl $-8, %esp
; FASTISEL-X86-NEXT: subl $8, %esp
; FASTISEL-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; FASTISEL-X86-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; FASTISEL-X86-NEXT: movlps %xmm0, (%esp)
; FASTISEL-X86-NEXT: movl (%esp), %eax
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; FASTISEL-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; FASTISEL-X86-NEXT: andl $2147483647, %edx # imm = 0x7FFFFFFF
; FASTISEL-X86-NEXT: movl %ebp, %esp
; FASTISEL-X86-NEXT: popl %ebp
; FASTISEL-X86-NEXT: retl
;
; GISEL-X86-LABEL: test_double_abs:
; GISEL-X86: # %bb.0:
; GISEL-X86-NEXT: movl $-1, %eax
; GISEL-X86-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %eax
; GISEL-X86-NEXT: andl {{[0-9]+}}(%esp), %edx
; GISEL-X86-NEXT: retl
%abs = tail call double @llvm.fabs.f64(double %arg)
ret double %abs
}
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