Skip to content

[AMDGPU] remove move instruction if there is no user of it #136735

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
May 3, 2025
Merged

[AMDGPU] remove move instruction if there is no user of it #136735

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -797,7 +797,7 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
dropInstructionKeepingImpDefs(*MovY);
MachineInstr *Next = &*std::next(MovT.getIterator());

if (T.isVirtual() && MRI->use_nodbg_empty(T)) {
if (MRI->use_nodbg_empty(T)) {
Copy link
Contributor

@mariusz-sikora-at-amd mariusz-sikora-at-amd May 5, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It looks like use_nodbg_empty is not tracing registers which are used as sub-registers (for Physical Registers)

e.g.

$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec  // this instruction will be removed
$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
$vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec

$vgpr3 = V_MOV_B32_e32 0, implicit $exec
$vgpr4_vgpr5 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec

vs.

$vgpr2 = V_MOV_B32_e32 killed $vgpr0, implicit $exec
$vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
$vgpr1 = V_MOV_B32_e32 $vgpr2, implicit $exec

$vgpr4 = V_MOV_B32_e32 $vgpr2, implicit $exec

Maybe we should also check if T is not marked as killed ?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@mariusz-sikora-at-amd Can you attach a complete test case here so I can check it? Thanks

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I agree - as far as I can see, the use list for physical registers does not include any aliasing registers, so the committed patch is not safe and should be reverted.

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Another reason we should remove use lists for physical registers

dropInstructionKeepingImpDefs(MovT);
} else {
Xop.setIsKill(false);
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/AMDGPU/v_swap_b16.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -32,12 +32,11 @@ define half @swap(half %a, half %b, i32 %i) {
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX11-FAKE16-NEXT: .LBB0_1: ; %loop
; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX11-FAKE16-NEXT: v_swap_b32 v1, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-FAKE16-NEXT: s_or_b32 s0, vcc_lo, s0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB0_1
; GFX11-FAKE16-NEXT: ; %bb.2: ; %ret
Expand Down Expand Up @@ -81,7 +80,7 @@ define half @swap(half %a, half %b, i32 %i) {
; GFX12-FAKE16-NEXT: s_mov_b32 s0, 0
; GFX12-FAKE16-NEXT: .LBB0_1: ; %loop
; GFX12-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_add_nc_u32 v2, -1, v2
; GFX12-FAKE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
; GFX12-FAKE16-NEXT: v_swap_b32 v1, v0
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
Expand Down
9 changes: 1 addition & 8 deletions llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,11 +1,9 @@
# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -passes=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

# GCN-LABEL: name: swap_phys_condensed
# GCN: bb.0:
# GCN-NEXT: liveins:
# GCN-NEXT: {{^[ ]*$}}
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
# GCN-NEXT: S_SETPC_B64_return
---
Expand All @@ -24,7 +22,6 @@ body: |
# GCN: bb.0:
# GCN-NEXT: liveins:
# GCN-NEXT: {{^[ ]*$}}
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr3 = V_MOV_B32_e32 killed $vgpr4, implicit $exec
# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
# GCN-NEXT: $vgpr5 = V_MOV_B32_e32 killed $vgpr6, implicit $exec
Expand All @@ -47,7 +44,6 @@ body: |
# GCN: bb.0:
# GCN-NEXT: liveins:
# GCN-NEXT: {{^[ ]*$}}
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
# GCN-NEXT: S_SETPC_B64_return
---
Expand All @@ -66,7 +62,6 @@ body: |
# GCN: bb.0:
# GCN-NEXT: liveins:
# GCN-NEXT: {{^[ ]*$}}
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
# GCN-NEXT: S_SETPC_B64_return
---
Expand All @@ -85,7 +80,6 @@ body: |
# GCN: bb.0:
# GCN-NEXT: liveins:
# GCN-NEXT: {{^[ ]*$}}
# GCN-NEXT: $vgpr4_vgpr5 = COPY $vgpr0_vgpr1
# GCN-NEXT: $vgpr0, $vgpr2 = V_SWAP_B32 $vgpr2, $vgpr0, implicit $exec
# GCN-NEXT: $vgpr1, $vgpr3 = V_SWAP_B32 $vgpr3, $vgpr1, implicit $exec
---
Expand Down Expand Up @@ -936,8 +930,7 @@ body: |
...

# GCN-LABEL: implicit_ops_mov_t_swap_b32
# GCN: $vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $vgpr2, implicit killed $vgpr1_vgpr2, implicit-def $vgpr1
# GCN-NEXT: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec
# GCN: $vgpr0, $vgpr1 = V_SWAP_B32 $vgpr1, $vgpr0, implicit $exec

---
name: implicit_ops_mov_t_swap_b32
Expand Down