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[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. #136762
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesAny kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register. Full diff: https://github.com/llvm/llvm-project/pull/136762.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp b/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
index 989e9d859d64f..aa8da1486faca 100644
--- a/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFoldMemOffset.cpp
@@ -274,6 +274,7 @@ bool RISCVFoldMemOffset::runOnMachineFunction(MachineFunction &MF) {
MemMI->getOperand(2).setImm(NewOffset);
MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg());
+ MRI.clearKillFlags(MI.getOperand(1).getReg());
MI.eraseFromParent();
}
}
diff --git a/llvm/test/CodeGen/RISCV/fold-mem-offset.mir b/llvm/test/CodeGen/RISCV/fold-mem-offset.mir
new file mode 100644
index 0000000000000..17cec6e6f8b9c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/fold-mem-offset.mir
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv32 -run-pass=riscv-fold-mem-offset -verify-machineinstrs | FileCheck %s
+
+---
+name: crash
+tracksRegLiveness: true
+noPhis: false
+isSSA: true
+noVRegs: false
+hasFakeUses: false
+body: |
+ bb.0:
+ liveins: $x10, $x11
+
+ ; CHECK-LABEL: name: crash
+ ; CHECK: liveins: $x10, $x11
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
+ ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 3
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD killed [[SLLI]], [[COPY1]]
+ ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 23
+ ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]]
+ ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD]], [[LUI]]
+ ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW killed [[ADD2]], 1792
+ ; CHECK-NEXT: [[LW1:%[0-9]+]]:gpr = LW killed [[ADD1]], 1796
+ ; CHECK-NEXT: $x10 = COPY [[LW]]
+ ; CHECK-NEXT: $x11 = COPY [[LW1]]
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %1:gpr = COPY $x11
+ %0:gpr = COPY $x10
+ %3:gpr = SLLI %1, 3
+ %4:gpr = ADD killed %3, %0
+ %5:gpr = LUI 23
+ %6:gpr = ADDI %5, 1792
+ %7:gpr = ADD %4, killed %6
+ %8:gpr = ADD %4, %5
+ %9:gpr = LW killed %8, 1792
+ %10:gpr = LW killed %7, 4
+ $x10 = COPY %9
+ $x11 = COPY %10
+ PseudoRET implicit $x10, implicit $x11
+...
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LGTM
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/202/builds/836 Here is the relevant piece of the build log for the reference
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…lvm#136762) Any kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register.
…lvm#136762) Any kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register.
…lvm#136762) Any kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register.
Any kill flags that were present for the old register are not valid for the replacement and the replacement may have extended the live range of the replacement register.