Revert "[X86][APX] Support peephole optimization with CCMP instruction (#129994)" #136796
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llvm#129994)" This reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example as below: C source code: ` if (a > 2 || (b && (a == 2))) { … } ` MIR before peephole optimization: ` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 3 JCC_1 %bb.6, 2, implicit $eflags JMP_1 %bb.3 ` Inputs: ` a = 1, b = 0. ` With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With same inputs, JCC instruction will fall through to the next instruction. It's not expected and the peephole optimization for CCMP instruction is not correct. ` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 JCC_1 %bb.6, 6, implicit $eflags JMP_1 %bb.3 `
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@llvm/pr-subscribers-backend-x86 Author: Feng Zou (fzou1) ChangesThis reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example as below: MIR before peephole optimization: Inputs: With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With same inputs, JCC instruction falls through to the next instruction. It's not expected behavior and the 2nd CCMP32ri should not be eliminated. Patch is 22.53 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/136796.diff 5 Files Affected:
diff --git a/llvm/lib/Target/X86/X86InstrConditionalCompare.td b/llvm/lib/Target/X86/X86InstrConditionalCompare.td
index ba8cf6cc3bc67..35af8405f1abe 100644
--- a/llvm/lib/Target/X86/X86InstrConditionalCompare.td
+++ b/llvm/lib/Target/X86/X86InstrConditionalCompare.td
@@ -36,7 +36,7 @@ class Ctest<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>:
//===----------------------------------------------------------------------===//
// CCMP Instructions
//
-let SchedRW = [WriteALU], isCompare = 1 in {
+let SchedRW = [WriteALU] in {
def CCMP8rr : Ccmp<0x38, MRMDestReg, Xi8, GR8, GR8>;
def CCMP16rr: Ccmp<0x39, MRMDestReg, Xi16, GR16, GR16>, PD;
def CCMP32rr: Ccmp<0x39, MRMDestReg, Xi32, GR32, GR32>;
@@ -55,7 +55,7 @@ let SchedRW = [WriteALU], isCompare = 1 in {
def CCMP64ri32: Ccmp<0x81, MRM7r, Xi64, GR64, i64i32imm>;
}
-let mayLoad = 1, isCompare = 1 in {
+let mayLoad = 1 in {
let SchedRW = [WriteALU.Folded] in {
def CCMP16mi8: Ccmp<0x83, MRM7m, Xi16, i16mem, i16i8imm>, PD;
def CCMP32mi8: Ccmp<0x83, MRM7m, Xi32, i32mem, i32i8imm>;
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 459e15031ee16..de29a76882148 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4875,10 +4875,6 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
case X86::CMP32ri:
case X86::CMP16ri:
case X86::CMP8ri:
- case X86::CCMP64ri32:
- case X86::CCMP32ri:
- case X86::CCMP16ri:
- case X86::CCMP8ri:
SrcReg = MI.getOperand(0).getReg();
SrcReg2 = 0;
if (MI.getOperand(1).isImm()) {
@@ -4976,18 +4972,6 @@ bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
}
return false;
}
- case X86::CCMP64ri32:
- case X86::CCMP32ri:
- case X86::CCMP16ri:
- case X86::CCMP8ri: {
- // The CCMP instruction should not be optimized if the scc/dfv in it is not
- // same as the one in previous CCMP instruction.
- if ((FlagI.getOpcode() != OI.getOpcode()) ||
- (OI.getOperand(2).getImm() != FlagI.getOperand(2).getImm()) ||
- (OI.getOperand(3).getImm() != FlagI.getOperand(3).getImm()))
- return false;
- [[fallthrough]];
- }
case X86::CMP64ri32:
case X86::CMP32ri:
case X86::CMP16ri:
diff --git a/llvm/test/CodeGen/X86/apx/ccmp.ll b/llvm/test/CodeGen/X86/apx/ccmp.ll
index e2e4e8df93149..7bd8aeea8863b 100644
--- a/llvm/test/CodeGen/X86/apx/ccmp.ll
+++ b/llvm/test/CodeGen/X86/apx/ccmp.ll
@@ -1300,75 +1300,5 @@ if.end: ; preds = %entry, %if.then
ret void
}
-define void @ccmp_continous_adjust_imm(i32 noundef %a, i32 noundef %b) {
-; CHECK-LABEL: ccmp_continous_adjust_imm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmpl $2, %edi # encoding: [0x83,0xff,0x02]
-; CHECK-NEXT: ccmpll {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0c,0x83,0xfe,0x02]
-; CHECK-NEXT: jg .LBB31_1 # encoding: [0x7f,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: .LBB31_1-1, kind: FK_PCRel_1
-; CHECK-NEXT: # %bb.2: # %if.then
-; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; CHECK-NEXT: jmp foo # TAILCALL
-; CHECK-NEXT: # encoding: [0xeb,A]
-; CHECK-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
-; CHECK-NEXT: .LBB31_1: # %if.end
-; CHECK-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: ccmp_continous_adjust_imm:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: cmpl $2, %edi # encoding: [0x83,0xff,0x02]
-; NDD-NEXT: ccmpll {dfv=} $2, %esi # encoding: [0x62,0xf4,0x04,0x0c,0x83,0xfe,0x02]
-; NDD-NEXT: jg .LBB31_1 # encoding: [0x7f,A]
-; NDD-NEXT: # fixup A - offset: 1, value: .LBB31_1-1, kind: FK_PCRel_1
-; NDD-NEXT: # %bb.2: # %if.then
-; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
-; NDD-NEXT: jmp foo # TAILCALL
-; NDD-NEXT: # encoding: [0xeb,A]
-; NDD-NEXT: # fixup A - offset: 1, value: foo-1, kind: FK_PCRel_1
-; NDD-NEXT: .LBB31_1: # %if.end
-; NDD-NEXT: retq # encoding: [0xc3]
-entry:
- %cmp = icmp slt i32 %a, 2
- %cmp1 = icmp slt i32 %b, 2
- %or.cond = and i1 %cmp, %cmp1
- %cmp3 = icmp slt i32 %b, 3
- %or.cond4 = and i1 %or.cond, %cmp3
- br i1 %or.cond4, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- tail call void (...) @foo()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- ret void
-}
-
-define i32 @ccmp_continous_nobranch_adjust_imm(i32 noundef %a, i32 noundef %b) {
-; CHECK-LABEL: ccmp_continous_nobranch_adjust_imm:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmpl $2, %esi # encoding: [0x83,0xfe,0x02]
-; CHECK-NEXT: ccmpgl {dfv=} $2, %edi # encoding: [0x62,0xf4,0x04,0x0f,0x83,0xff,0x02]
-; CHECK-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
-; CHECK-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; CHECK-NEXT: retq # encoding: [0xc3]
-;
-; NDD-LABEL: ccmp_continous_nobranch_adjust_imm:
-; NDD: # %bb.0: # %entry
-; NDD-NEXT: cmpl $2, %esi # encoding: [0x83,0xfe,0x02]
-; NDD-NEXT: ccmpgl {dfv=} $2, %edi # encoding: [0x62,0xf4,0x04,0x0f,0x83,0xff,0x02]
-; NDD-NEXT: setge %al # encoding: [0x0f,0x9d,0xc0]
-; NDD-NEXT: movzbl %al, %eax # encoding: [0x0f,0xb6,0xc0]
-; NDD-NEXT: retq # encoding: [0xc3]
-entry:
- %cmp = icmp sgt i32 %a, 1
- %cmp1 = icmp slt i32 %b, 2
- %cmp2 = icmp slt i32 %b, 3
- %or1 = or i1 %cmp, %cmp1
- %or2 = or i1 %or1, %cmp2
- %. = zext i1 %or2 to i32
- ret i32 %.
-}
-
declare dso_local void @foo(...)
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/apx/optimize-compare-ccmp.mir b/llvm/test/CodeGen/X86/apx/optimize-compare-ccmp.mir
deleted file mode 100644
index f766ec00cbc3c..0000000000000
--- a/llvm/test/CodeGen/X86/apx/optimize-compare-ccmp.mir
+++ /dev/null
@@ -1,396 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -o - %s -mtriple=x86_64-- -run-pass peephole-opt | FileCheck %s
-
----
-name: opt_redundant_flags_adjusted_imm_0
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_0
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 1, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 == 1
- CCMP64ri32 %0, 1, 2, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags
- ; CCMP+SETCC %0 >= 2; CCMP can be removed.
- CCMP64ri32 %0, 2, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 >=s 2 --> %0 >s 1
- $bl = SETCCr 13, implicit $eflags
- ; %0 >=u 2 --> %0 >u 1
- $bl = SETCCr 3, implicit $eflags
- ; %0 <s 2 --> %0 <=s 1
- $bl = SETCCr 12, implicit $eflags
- ; %0 <u 2 --> %0 <=u 1
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_1
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_1
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 42, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 5, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 != 42
- CCMP64ri32 %0, 42, 2, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 5, implicit $eflags
- ; CCMP+SETCC %0 > 41; CCMP can be removed.
- CCMP64ri32 %0, 41, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 >s 41 --> %0 >=s 42
- $bl = SETCCr 15, implicit $eflags
- ; %0 >u 41 --> %0 >=u 42
- $bl = SETCCr 7, implicit $eflags
- ; %0 <=s 41 --> %0 <s 42
- $bl = SETCCr 14, implicit $eflags
- ; %0 <=u 41 --> %0 <u 42
- $bl = SETCCr 6, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_2
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_2
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 1, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
- %0:gr64 = COPY $rsi
- %1:gr64 = MOV64ri 1
- ; CCMP+SETCC %0 == 1
- ; CCMP64rr will be optimized to CCMP64ri32 in the peephole optimiztion pass
- CCMP64rr %0, %1, 2, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags
- ; CCMP+SETCC %0 >= 2; CCMP can be removed.
- CCMP64ri32 %0, 2, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 >=s 2 --> %0 >s 1
- $bl = SETCCr 13, implicit $eflags
- ; %0 >=u 2 --> %0 >u 1
- $bl = SETCCr 3, implicit $eflags
- ; %0 <s 2 --> %0 <=s 1
- $bl = SETCCr 12, implicit $eflags
- ; %0 <u 2 --> %0 <=u 1
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_3
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_3
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CMP64ri32 [[COPY]], 1, implicit-def $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 7, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CMP+SETCC %0 == 1
- CMP64ri32 %0, 1, implicit-def $eflags
- $cl = SETCCr 4, implicit $eflags
- ; CCMP+SETCC %0 >= 2; CCMP can be removed.
- CCMP64ri32 %0, 2, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 >=s 2 --> %0 >s 1
- $bl = SETCCr 13, implicit $eflags
- ; %0 >=u 2 --> %0 >u 1
- $bl = SETCCr 3, implicit $eflags
- ; %0 <s 2 --> %0 <=s 1
- $bl = SETCCr 12, implicit $eflags
- ; %0 <u 2 --> %0 <=u 1
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_0
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_0
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 42, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 41, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 4, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 <s 1
- CCMP64ri32 %0, 42, 2, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags
- ; CCMP should not be removed.
- CCMP64ri32 %0, 41, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 == 41
- $bl = SETCCr 4, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_1
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_1
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK-NEXT: CCMP32ri [[COPY]], 2147483647, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 2147483647, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP32ri [[COPY]], 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
- %0:gr32 = COPY $esi
- ; CCMP+SETCC %0 == INT32_MAX
- CCMP32ri %0, 2147483647, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP32ri %0, -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 <s INT32_MIN
- $bl = SETCCr 12, implicit $eflags
-
- CCMP32ri %0, 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP32ri %0, -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 12, implicit $eflags
-
- CCMP32ri %0, 2147483647, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP32ri %0, -2147483648, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 13, implicit $eflags
-
- CCMP32ri %0, 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP32ri %0, 0, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 2, implicit $eflags
-
- CCMP32ri %0, 4294967295, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP32ri %0, 0, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 3, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_2
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_2
- ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $cx
- ; CHECK-NEXT: CCMP16ri [[COPY]], -32768, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 32767, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 65535, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 32767, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 15, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], -32768, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 32767, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 14, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 65535, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP16ri [[COPY]], 65535, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 6, implicit $eflags
- %0:gr16 = COPY $cx
- ; CCMP+SETCC %0 == INT16_MIN
- CCMP16ri %0, -32768, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP16ri %0, 32767, 2, 5, implicit-def $eflags, implicit $eflags
- ; %0 >s INT16_MAX
- $bl = SETCCr 15, implicit $eflags
-
- CCMP16ri %0, 65535, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP16ri %0, 32767, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 15, implicit $eflags
-
- CCMP16ri %0, -32768, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP16ri %0, 32767, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 14, implicit $eflags
-
- CCMP16ri %0, 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP16ri %0, 65535, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 4, implicit $eflags
-
- CCMP16ri %0, 0, 2, 5, implicit-def $eflags, implicit $eflags
- ; CCMP should not be removed.
- CCMP16ri %0, 65535, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 6, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_3
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_3
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 1, 2, 7, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 2, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 == 1
- CCMP64ri32 %0, 1, 2, 7, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags, implicit $eflags
- ; CCMP+SETCC %0 >= 2; CCMP should not be removed as the scc and dfv is
- ; different.
- CCMP64ri32 %0, 2, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 13, implicit $eflags
- $bl = SETCCr 3, implicit $eflags
- $bl = SETCCr 12, implicit $eflags
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_4
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_4
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 1, 5, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags, implicit $eflags
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 2, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 == 1
- CCMP64ri32 %0, 1, 5, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags, implicit $eflags
- ; CCMP+SETCC %0 >= 2; CCMP should not be removed as the scc and dfv is
- ; different.
- CCMP64ri32 %0, 2, 2, 5, implicit-def $eflags, implicit $eflags
- $bl = SETCCr 13, implicit $eflags
- $bl = SETCCr 3, implicit $eflags
- $bl = SETCCr 12, implicit $eflags
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_redundant_flags_adjusted_imm_noopt_5
-body: |
- bb.0:
- ; CHECK-LABEL: name: opt_redundant_flags_adjusted_imm_noopt_5
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK-NEXT: CCMP64ri32 [[COPY]], 1, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: $cl = SETCCr 4, implicit $eflags
- ; CHECK-NEXT: CMP64ri32 [[COPY]], 2, implicit-def $eflags
- ; CHECK-NEXT: $bl = SETCCr 13, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 3, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 12, implicit $eflags
- ; CHECK-NEXT: $bl = SETCCr 2, implicit $eflags
- %0:gr64 = COPY $rsi
- ; CCMP+SETCC %0 == 1
- CCMP64ri32 %0, 1, 2, 5, implicit-def $eflags, implicit $eflags
- $cl = SETCCr 4, implicit $eflags
- ; CMP+SETCC %0 >= 2; CMP cannot be removed.
- CMP64ri32 %0, 2, implicit-def $eflags
- ; %0 >=s 2 --> %0 >s 1
- $bl = SETCCr 13, implicit $eflags
- ; %0 >=u 2 --> %0 >u 1
- $bl = SETCCr 3, implicit $eflags
- ; %0 <s 2 --> %0 <=s 1
- $bl = SETCCr 12, implicit $eflags
- ; %0 <u 2 --> %0 <=u 1
- $bl = SETCCr 2, implicit $eflags
-...
----
-name: opt_adjusted_imm_multiple_blocks
-body: |
- ; CHECK-LABEL: name: opt_adjusted_imm_multiple_blocks
- ; CHECK: bb.0:
- ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax
- ; CHECK-NEXT: CCMP32ri [[COPY]], 20, 2, 5, implicit-def $eflags, implicit $eflags
- ; CHECK-NEXT: JCC_1 %bb.1, 4, implicit $eflags
- ; CHECK-NEXT: JMP_1 %bb.3
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
- ; CHECK-NEXT: liveins: $eflags
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: JCC_1 %bb.2, 15, implicit $eflags
- ; CHECK-NEXT: JMP_1 %bb.3
- ; CHECK...
[truncated]
|
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/52/builds/7842 Here is the relevant piece of the build log for the reference |
IanWood1
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May 6, 2025
llvm#129994)" (llvm#136796) This reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example below: C source code: ``` if (a > 2 || (b && (a == 2))) { … } ``` MIR before peephole optimization: ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 2 (transformed to a < 3) JCC_1 %bb.6, 2, implicit $eflags JMP_1 %bb.3 ``` Inputs: ``` a = 1, b = 0. ``` With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With the same inputs, JCC instruction falls through to the next instruction. It's not expected and the 2nd CCMP32ri should not be eliminated. ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 JCC_1 %bb.6, 6, implicit $eflags JMP_1 %bb.3 ```
IanWood1
pushed a commit
to IanWood1/llvm-project
that referenced
this pull request
May 6, 2025
llvm#129994)" (llvm#136796) This reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example below: C source code: ``` if (a > 2 || (b && (a == 2))) { … } ``` MIR before peephole optimization: ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 2 (transformed to a < 3) JCC_1 %bb.6, 2, implicit $eflags JMP_1 %bb.3 ``` Inputs: ``` a = 1, b = 0. ``` With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With the same inputs, JCC instruction falls through to the next instruction. It's not expected and the 2nd CCMP32ri should not be eliminated. ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 JCC_1 %bb.6, 6, implicit $eflags JMP_1 %bb.3 ```
IanWood1
pushed a commit
to IanWood1/llvm-project
that referenced
this pull request
May 6, 2025
llvm#129994)" (llvm#136796) This reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example below: C source code: ``` if (a > 2 || (b && (a == 2))) { … } ``` MIR before peephole optimization: ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 2 (transformed to a < 3) JCC_1 %bb.6, 2, implicit $eflags JMP_1 %bb.3 ``` Inputs: ``` a = 1, b = 0. ``` With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With the same inputs, JCC instruction falls through to the next instruction. It's not expected and the 2nd CCMP32ri should not be eliminated. ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 JCC_1 %bb.6, 6, implicit $eflags JMP_1 %bb.3 ```
Ankur-0429
pushed a commit
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that referenced
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May 9, 2025
llvm#129994)" (llvm#136796) This reverts commit 7ae7585. There is a problem with peephole optimization for CCMP instruction. See the example below: C source code: ``` if (a > 2 || (b && (a == 2))) { … } ``` MIR before peephole optimization: ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 2 (transformed to a < 3) JCC_1 %bb.6, 2, implicit $eflags JMP_1 %bb.3 ``` Inputs: ``` a = 1, b = 0. ``` With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB. But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With the same inputs, JCC instruction falls through to the next instruction. It's not expected and the 2nd CCMP32ri should not be eliminated. ``` TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2 JCC_1 %bb.6, 6, implicit $eflags JMP_1 %bb.3 ```
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This reverts commit 7ae7585.
There is a problem with peephole optimization for CCMP instruction. See the example below:
C source code:
MIR before peephole optimization:
Inputs:
With the inputs above, the expected behavior is to jump to %bb.6 BB. After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the following CCMP32ri instruction (for a==2 condition) which skips compare a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags satisfies the SCC condition in the 2nd CCMP32ri instruction which compares a(%30) with 3. It sets CF to 1 in eflags and the JCC instruction jumps to %bb.6 BB.
But after adding CCMP support, peephole optimization eliminates the 2nd CCMP32ri instruction and updates the condition of JCC instruction to "BE" from "B". With the same inputs, JCC instruction falls through to the next instruction. It's not expected and the 2nd CCMP32ri should not be eliminated.