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[SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load_*ext_8/atomic_load_*ext_16 where possible. #137279

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Merged
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Apr 25, 2025
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[SelectionDAG][Targets] Replace atomic_load_8/atomic_load_16 with atomic_load_*ext_8/atomic_load_*ext_16 where possible. #137279

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5 changes: 5 additions & 0 deletions llvm/include/llvm/Target/TargetSelectionDAG.td
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Expand Up @@ -1946,6 +1946,11 @@ def atomic_load_azext_16 : PatFrags<(ops node:$op),
[(atomic_load_aext_16 node:$op),
(atomic_load_zext_16 node:$op)]>;

// Atomic load which zeroes or anyextends the high bits.
def atomic_load_azext_32 : PatFrags<(ops node:$op),
[(atomic_load_aext_32 node:$op),
(atomic_load_zext_32 node:$op)]>;

// Atomic load which sign extends or anyextends the high bits.
def atomic_load_asext_8 : PatFrags<(ops node:$op),
[(atomic_load_aext_8 node:$op),
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/AArch64InstrAtomics.td
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Expand Up @@ -51,9 +51,9 @@ class seq_cst_load<PatFrags base>
let Predicates = [HasRCPC] in {
// v8.3 Release Consistent Processor Consistent support, optional in v8.2.
// 8-bit loads
def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
def : Pat<(acquiring_load<atomic_load_azext_8> GPR64sp:$ptr), (LDAPRB GPR64sp:$ptr)>;
// 16-bit loads
def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
def : Pat<(acquiring_load<atomic_load_azext_16> GPR64sp:$ptr), (LDAPRH GPR64sp:$ptr)>;
// 32-bit loads
def : Pat<(acquiring_load<atomic_load_32> GPR64sp:$ptr), (LDAPRW GPR64sp:$ptr)>;
// 64-bit loads
Expand Down
12 changes: 8 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
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Expand Up @@ -502,10 +502,6 @@ def zextloadi16_#as : PatFrag<(ops node:$ptr), (zextloadi16 node:$ptr)> {
let IsLoad = 1;
}

def atomic_load_8_#as : PatFrag<(ops node:$ptr), (atomic_load_8 node:$ptr)> {
let IsAtomic = 1;
}

def atomic_load_16_#as : PatFrag<(ops node:$ptr), (atomic_load_16 node:$ptr)> {
let IsAtomic = 1;
}
Expand All @@ -526,6 +522,10 @@ def atomic_load_sext_8_#as : PatFrag<(ops node:$ptr), (atomic_load_sext_8 node:$
let IsAtomic = 1;
}

def atomic_load_aext_8_#as : PatFrag<(ops node:$ptr), (atomic_load_aext_8 node:$ptr)> {
let IsAtomic = 1;
}

def atomic_load_zext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_zext_16 node:$ptr)> {
let IsAtomic = 1;
}
Expand All @@ -534,6 +534,10 @@ def atomic_load_sext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_sext_16 node
let IsAtomic = 1;
}

def atomic_load_aext_16_#as : PatFrag<(ops node:$ptr), (atomic_load_aext_16 node:$ptr)> {
let IsAtomic = 1;
}

} // End let AddressSpaces
} // End foreach as

Expand Down
7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/BUFInstructions.td
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Expand Up @@ -953,11 +953,12 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads_Lds <
"buffer_load_dwordx4", v4i32, /*LDSPred=*/HasGFX950Insts
>;

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_aext_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_zext_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_16_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_aext_16_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_zext_16_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_aext_8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_zext_8_global>;
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One pattern had to become two here to cover both types of extends.

defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_16_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, extloadi8_global>;
defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, zextloadi8_global>;
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/DSInstructions.td
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Expand Up @@ -853,14 +853,14 @@ foreach vt = Reg32Types.types in {
defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
}

defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_8_local">;
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_8_local">;
defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_aext_8_local">;
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_aext_8_local">;
defm : DSReadPat_t16 <DS_READ_U8, i16, "atomic_load_zext_8_local">;
defm : DSReadPat_mc <DS_READ_U8, i32, "atomic_load_zext_8_local">;
defm : DSReadPat_t16 <DS_READ_I8, i16, "atomic_load_sext_8_local">;
defm : DSReadPat_mc <DS_READ_I8, i32, "atomic_load_sext_8_local">;
defm : DSReadPat_t16 <DS_READ_U16, i16, "atomic_load_16_local">;
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_16_local">;
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_aext_16_local">;
defm : DSReadPat_mc <DS_READ_U16, i32, "atomic_load_zext_16_local">;
defm : DSReadPat_mc <DS_READ_I16, i32, "atomic_load_sext_16_local">;
defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
Expand Down
13 changes: 6 additions & 7 deletions llvm/lib/Target/AMDGPU/FLATInstructions.td
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Expand Up @@ -1536,14 +1536,13 @@ multiclass ScratchFLATLoadPats_D16_t16<string inst, SDPatternOperator node, Valu

let OtherPredicates = [HasFlatAddressSpace] in {

def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i16>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_aext_8_flat, i16>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_zext_8_flat, i16>;
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_aext_16_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i16>;
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_zext_16_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_zext_16_flat, i16>;
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This pattern looked to be impossible to match. It's a zextload with i16 memory and result type.

def : FlatLoadPat <FLAT_LOAD_UBYTE, extloadi8_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_UBYTE, zextloadi8_flat, i32>;
def : FlatLoadPat <FLAT_LOAD_SBYTE, sextloadi8_flat, i32>;
Expand Down Expand Up @@ -1678,11 +1677,11 @@ def : FlatLoadPat_D16 <FLAT_LOAD_SHORT_D16, load_d16_lo_flat, v2f16>;

let OtherPredicates = [HasFlatGlobalInsts] in {

defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_aext_8_global, i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_zext_8_global, i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_aext_16_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i16>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i32>;
defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_zext_16_global, i16>;
Expand Down
26 changes: 20 additions & 6 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.td
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Expand Up @@ -373,10 +373,10 @@ def atomic_load_sext_glue :
let IsSignExtLoad = true;
}

def atomic_load_8_glue : PatFrag<(ops node:$ptr),
(AMDGPUatomic_ld_glue node:$ptr)> {
let IsAtomic = 1;
let MemoryVT = i8;
def atomic_load_aext_glue :
PatFrag<(ops node:$ptr), (AMDGPUatomic_ld_glue node:$ptr)> {
let IsAtomic = true; // FIXME: Should be IsLoad and/or IsAtomic?
let IsAnyExtLoad = true;
}

def atomic_load_16_glue : PatFrag<(ops node:$ptr),
Expand Down Expand Up @@ -409,6 +409,12 @@ def atomic_load_sext_8_glue : PatFrag<(ops node:$ptr),
let MemoryVT = i8;
}

def atomic_load_aext_8_glue : PatFrag<(ops node:$ptr),
(atomic_load_aext_glue node:$ptr)> {
let IsAtomic = 1;
let MemoryVT = i8;
}

def atomic_load_zext_16_glue : PatFrag<(ops node:$ptr),
(atomic_load_zext_glue node:$ptr)> {
let IsAtomic = 1;
Expand All @@ -421,6 +427,12 @@ def atomic_load_sext_16_glue : PatFrag<(ops node:$ptr),
let MemoryVT = i16;
}

def atomic_load_aext_16_glue : PatFrag<(ops node:$ptr),
(atomic_load_aext_glue node:$ptr)> {
let IsAtomic = 1;
let MemoryVT = i16;
}

def extload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr)> {
let IsLoad = 1;
let IsAnyExtLoad = 1;
Expand Down Expand Up @@ -494,8 +506,6 @@ def load_align16_local_m0 : PatFrag<(ops node:$ptr),
}

let IsAtomic = 1, AddressSpaces = LoadAddress_local.AddrSpaces in {
def atomic_load_8_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_8_glue node:$ptr)>;
def atomic_load_16_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_16_glue node:$ptr)>;
def atomic_load_32_local_m0 : PatFrag<(ops node:$ptr),
Expand All @@ -507,10 +517,14 @@ def atomic_load_zext_8_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_zext_8_glue node:$ptr)>;
def atomic_load_sext_8_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_sext_8_glue node:$ptr)>;
def atomic_load_aext_8_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_aext_8_glue node:$ptr)>;
def atomic_load_zext_16_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_zext_16_glue node:$ptr)>;
def atomic_load_sext_16_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_sext_16_glue node:$ptr)>;
def atomic_load_aext_16_local_m0 : PatFrag<(ops node:$ptr),
(atomic_load_aext_16_glue node:$ptr)>;
} // End let AddressSpaces = LoadAddress_local.AddrSpaces


Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMInstrInfo.td
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Expand Up @@ -5376,14 +5376,14 @@ def : ARMPat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
def : ARMPat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
(STLEXH GPR:$Rt, addr_offset_none:$addr)>;

class acquiring_load<PatFrag base>
class acquiring_load<PatFrags base>
: PatFrag<(ops node:$ptr), (base node:$ptr), [{
AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getSuccessOrdering();
return isAcquireOrStronger(Ordering);
}]>;

def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
def atomic_load_azext_acquire_8 : acquiring_load<atomic_load_azext_8>;
def atomic_load_azext_acquire_16 : acquiring_load<atomic_load_azext_16>;
def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;

class releasing_store<PatFrag base>
Expand All @@ -5397,8 +5397,8 @@ def atomic_store_release_16 : releasing_store<atomic_store_16>;
def atomic_store_release_32 : releasing_store<atomic_store_32>;

let AddedComplexity = 8 in {
def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
Expand Down Expand Up @@ -6214,11 +6214,11 @@ def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
(SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;

// Atomic load/store patterns
def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
def : ARMPat<(atomic_load_azext_8 ldst_so_reg:$src),
(LDRBrs ldst_so_reg:$src)>;
def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
def : ARMPat<(atomic_load_azext_8 addrmode_imm12:$src),
(LDRBi12 addrmode_imm12:$src)>;
def : ARMPat<(atomic_load_16 addrmode3:$src),
def : ARMPat<(atomic_load_azext_16 addrmode3:$src),
(LDRH addrmode3:$src)>;
def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
(LDRrs ldst_so_reg:$src)>;
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/ARM/ARMInstrThumb.td
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Expand Up @@ -1697,13 +1697,13 @@ def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
(tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;

def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
def : T1Pat<(atomic_load_azext_8 t_addrmode_is1:$src),
(tLDRBi t_addrmode_is1:$src)>;
def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
def : T1Pat<(atomic_load_azext_8 t_addrmode_rr:$src),
(tLDRBr t_addrmode_rr:$src)>;
def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
def : T1Pat<(atomic_load_azext_16 t_addrmode_is2:$src),
(tLDRHi t_addrmode_is2:$src)>;
def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
def : T1Pat<(atomic_load_azext_16 t_addrmode_rr:$src),
(tLDRHr t_addrmode_rr:$src)>;
def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
(tLDRi t_addrmode_is4:$src)>;
Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/ARM/ARMInstrThumb2.td
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Expand Up @@ -4899,17 +4899,17 @@ def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)),
Requires<[HasDSP, IsThumb2]>;

// Atomic load/store patterns
def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr),
def : T2Pat<(atomic_load_azext_8 t2addrmode_imm12:$addr),
(t2LDRBi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr),
def : T2Pat<(atomic_load_azext_8 t2addrmode_negimm8:$addr),
(t2LDRBi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr),
def : T2Pat<(atomic_load_azext_8 t2addrmode_so_reg:$addr),
(t2LDRBs t2addrmode_so_reg:$addr)>;
def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr),
def : T2Pat<(atomic_load_azext_16 t2addrmode_imm12:$addr),
(t2LDRHi12 t2addrmode_imm12:$addr)>;
def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr),
def : T2Pat<(atomic_load_azext_16 t2addrmode_negimm8:$addr),
(t2LDRHi8 t2addrmode_negimm8:$addr)>;
def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr),
def : T2Pat<(atomic_load_azext_16 t2addrmode_so_reg:$addr),
(t2LDRHs t2addrmode_so_reg:$addr)>;
def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr),
(t2LDRi12 t2addrmode_imm12:$addr)>;
Expand Down Expand Up @@ -4937,8 +4937,8 @@ def : T2Pat<(atomic_store_32 GPR:$val, t2addrmode_so_reg:$addr),
(t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;

let AddedComplexity = 8, Predicates = [IsThumb, HasAcquireRelease, HasV7Clrex] in {
def : Pat<(atomic_load_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
def : Pat<(atomic_load_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
def : Pat<(atomic_load_azext_acquire_8 addr_offset_none:$addr), (t2LDAB addr_offset_none:$addr)>;
def : Pat<(atomic_load_azext_acquire_16 addr_offset_none:$addr), (t2LDAH addr_offset_none:$addr)>;
def : Pat<(atomic_load_acquire_32 addr_offset_none:$addr), (t2LDA addr_offset_none:$addr)>;
def : Pat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (t2STLB GPR:$val, addr_offset_none:$addr)>;
def : Pat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (t2STLH GPR:$val, addr_offset_none:$addr)>;
Expand Down
20 changes: 10 additions & 10 deletions llvm/lib/Target/Hexagon/HexagonPatterns.td
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Expand Up @@ -2130,7 +2130,7 @@ def sextloadv4i8: PatFrag<(ops node:$ptr), (sextload node:$ptr), [{

// Patterns to select load-indexed: Rs + Off.
// - frameindex [+ imm],
multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
multiclass Loadxfi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
InstHexagon MI> {
def: Pat<(VT (Load (add (i32 AddrFI:$fi), ImmPred:$Off))),
(VT (MI AddrFI:$fi, imm:$Off))>;
Expand All @@ -2141,7 +2141,7 @@ multiclass Loadxfi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,

// Patterns to select load-indexed: Rs + Off.
// - base reg [+ imm]
multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
multiclass Loadxgi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
InstHexagon MI> {
def: Pat<(VT (Load (add I32:$Rs, ImmPred:$Off))),
(VT (MI IntRegs:$Rs, imm:$Off))>;
Expand All @@ -2151,7 +2151,7 @@ multiclass Loadxgi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
}

// Patterns to select load-indexed: Rs + Off. Combines Loadxfi + Loadxgi.
multiclass Loadxi_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
multiclass Loadxi_pat<PatFrags Load, ValueType VT, PatLeaf ImmPred,
InstHexagon MI> {
defm: Loadxfi_pat<Load, VT, ImmPred, MI>;
defm: Loadxgi_pat<Load, VT, ImmPred, MI>;
Expand Down Expand Up @@ -2221,7 +2221,7 @@ class Loadxum_pat<PatFrag Load, ValueType VT, PatFrag ImmPred, PatFrag ValueMod,
(VT (ValueMod (MI IntRegs:$Rt, imm:$u2, ImmPred:$Addr)))>;

// Pattern to select load absolute.
class Loada_pat<PatFrag Load, ValueType VT, PatFrag Addr, InstHexagon MI>
class Loada_pat<PatFrags Load, ValueType VT, PatFrag Addr, InstHexagon MI>
: Pat<(VT (Load Addr:$addr)), (MI Addr:$addr)>;

// Pattern to select load absolute with value modifier.
Expand Down Expand Up @@ -2256,8 +2256,8 @@ let AddedComplexity = 20 in {
defm: Loadxi_pat<load, f64, anyimm3, L2_loadrd_io>;
// No sextloadi1.

defm: Loadxi_pat<atomic_load_8 , i32, anyimm0, L2_loadrub_io>;
defm: Loadxi_pat<atomic_load_16, i32, anyimm1, L2_loadruh_io>;
defm: Loadxi_pat<atomic_load_azext_8 , i32, anyimm0, L2_loadrub_io>;
defm: Loadxi_pat<atomic_load_azext_16, i32, anyimm1, L2_loadruh_io>;
defm: Loadxi_pat<atomic_load_32, i32, anyimm2, L2_loadri_io>;
defm: Loadxi_pat<atomic_load_64, i64, anyimm3, L2_loadrd_io>;
}
Expand Down Expand Up @@ -2418,8 +2418,8 @@ let AddedComplexity = 60 in {
def: Loada_pat<load, f32, anyimm2, PS_loadriabs>;
def: Loada_pat<load, f64, anyimm3, PS_loadrdabs>;

def: Loada_pat<atomic_load_8, i32, anyimm0, PS_loadrubabs>;
def: Loada_pat<atomic_load_16, i32, anyimm1, PS_loadruhabs>;
def: Loada_pat<atomic_load_azext_8, i32, anyimm0, PS_loadrubabs>;
def: Loada_pat<atomic_load_azext_16, i32, anyimm1, PS_loadruhabs>;
def: Loada_pat<atomic_load_32, i32, anyimm2, PS_loadriabs>;
def: Loada_pat<atomic_load_64, i64, anyimm3, PS_loadrdabs>;
}
Expand Down Expand Up @@ -2463,8 +2463,8 @@ let AddedComplexity = 100 in {
def: Loada_pat<load, f32, addrgp, L2_loadrigp>;
def: Loada_pat<load, f64, addrgp, L2_loadrdgp>;

def: Loada_pat<atomic_load_8, i32, addrgp, L2_loadrubgp>;
def: Loada_pat<atomic_load_16, i32, addrgp, L2_loadruhgp>;
def: Loada_pat<atomic_load_azext_8, i32, addrgp, L2_loadrubgp>;
def: Loada_pat<atomic_load_azext_16, i32, addrgp, L2_loadruhgp>;
def: Loada_pat<atomic_load_32, i32, addrgp, L2_loadrigp>;
def: Loada_pat<atomic_load_64, i64, addrgp, L2_loadrdgp>;
}
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Lanai/LanaiInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -845,7 +845,7 @@ def : Pat<(extloadi16 ADDRspls:$src), (i32 (LDHz_RI ADDRspls:$src))>;
// Loads up to 32-bits are already atomic.
// TODO: This is a workaround for a particular failing case and should be
// handled more generally.
def : Pat<(atomic_load_8 ADDRspls:$src), (i32 (LDBz_RI ADDRspls:$src))>;
def : Pat<(atomic_load_azext_8 ADDRspls:$src), (i32 (LDBz_RI ADDRspls:$src))>;

// GlobalAddress, ExternalSymbol, Jumptable, ConstantPool
def : Pat<(LanaiHi tglobaladdr:$dst), (MOVHI tglobaladdr:$dst)>;
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9 changes: 5 additions & 4 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
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Expand Up @@ -1779,7 +1779,7 @@ def : Pat<(bitreverse (bswap GPR:$rj)), (BITREV_8B GPR:$rj)>;

/// Loads

multiclass LdPat<PatFrag LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
multiclass LdPat<PatFrags LoadOp, LAInst Inst, ValueType vt = GRLenVT> {
def : Pat<(vt (LoadOp BaseAddr:$rj)), (Inst BaseAddr:$rj, 0)>;
def : Pat<(vt (LoadOp (AddrConstant GPR:$rj, simm12:$imm12))),
(Inst GPR:$rj, simm12:$imm12)>;
Expand Down Expand Up @@ -1890,9 +1890,10 @@ def : Pat<(atomic_fence 5, timm), (DBAR 0b10010)>; // release
def : Pat<(atomic_fence 6, timm), (DBAR 0b10000)>; // acqrel
def : Pat<(atomic_fence 7, timm), (DBAR 0b10000)>; // seqcst

defm : LdPat<atomic_load_8, LD_B>;
defm : LdPat<atomic_load_16, LD_H>;
defm : LdPat<atomic_load_32, LD_W>;
defm : LdPat<atomic_load_asext_8, LD_B>;
defm : LdPat<atomic_load_asext_16, LD_H>;
defm : LdPat<atomic_load_32, LD_W>, Requires<[IsLA32]>;
defm : LdPat<atomic_load_asext_32, LD_W>, Requires<[IsLA64]>;

class release_seqcst_store<PatFrag base>
: PatFrag<(ops node:$val, node:$ptr), (base node:$val, node:$ptr), [{
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