[RISCV] Check the VT for R and cR inline asm constraints is 2*xlen.

[topperc]

Fixes #137726.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

Fixes #137726.

---

Full diff: https://github.com/llvm/llvm-project/pull/137749.diff

2 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+7-2)
• (modified) llvm/test/CodeGen/RISCV/inline-asm-invalid.ll (+50-2)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 722dcbbc6dd53..d205c25e73056 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22532,7 +22532,10 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       }
       break;
     case 'R':
-      return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
+      if (((VT == MVT::i64 || VT == MVT::f64) && !Subtarget.is64Bit()) ||
+          (VT == MVT::i128 && Subtarget.is64Bit()))
+        return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
+      break;
     default:
       break;
     }
@@ -22574,7 +22577,9 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     if (!VT.isVector())
       return std::make_pair(0U, &RISCV::GPRCRegClass);
   } else if (Constraint == "cR") {
-    return std::make_pair(0U, &RISCV::GPRPairCRegClass);
+    if (((VT == MVT::i64 || VT == MVT::f64) && !Subtarget.is64Bit()) ||
+        (VT == MVT::i128 && Subtarget.is64Bit()))
+      return std::make_pair(0U, &RISCV::GPRPairCRegClass);
   } else if (Constraint == "cf") {
     if (VT == MVT::f16) {
       if (Subtarget.hasStdExtZfhmin())
diff --git a/llvm/test/CodeGen/RISCV/inline-asm-invalid.ll b/llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
index deffa177c5e6b..8d90cd1d9c510 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
@@ -1,5 +1,5 @@
-; RUN: not llc -mtriple=riscv32 < %s 2>&1 | FileCheck %s
-; RUN: not llc -mtriple=riscv64 < %s 2>&1 | FileCheck %s
+; RUN: not llc -mtriple=riscv32 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK32
+; RUN: not llc -mtriple=riscv64 < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK64
 
 define void @constraint_I() {
 ; CHECK: error: value out of range for constraint 'I'
@@ -62,3 +62,51 @@ define void @constraint_cr_scalable_vec() nounwind {
   tail call void asm "add a0, a0, $0", "^cr"(<vscale x 4 x i32> zeroinitializer)
   ret void
 }
+
+define void @constraint_R_i32() nounwind {
+; CHECK32: error: couldn't allocate input reg for constraint 'R'
+  tail call void asm "add a0, a0, $0", "R"(i32 zeroinitializer)
+  ret void
+}
+
+define void @constraint_R_i64() nounwind {
+; CHECK64: error: couldn't allocate input reg for constraint 'R'
+  tail call void asm "add a0, a0, $0", "R"(i64 zeroinitializer)
+  ret void
+}
+
+define void @constraint_R_i128() nounwind {
+; CHECK32: error: couldn't allocate input reg for constraint 'R'
+  tail call void asm "add a0, a0, $0", "R"(i128 zeroinitializer)
+  ret void
+}
+
+define void @constraint_R_i256() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'R'
+  tail call void asm "add a0, a0, $0", "R"(i256 zeroinitializer)
+  ret void
+}
+
+define void @constraint_cR_i32() nounwind {
+; CHECK32: error: couldn't allocate input reg for constraint 'cR'
+  tail call void asm "add a0, a0, $0", "^cR"(i32 zeroinitializer)
+  ret void
+}
+
+define void @constraint_cR_i64() nounwind {
+; CHECK64: error: couldn't allocate input reg for constraint 'cR'
+  tail call void asm "add a0, a0, $0", "^cR"(i64 zeroinitializer)
+  ret void
+}
+
+define void @constraint_cR_i128() nounwind {
+; CHECK32: error: couldn't allocate input reg for constraint 'cR'
+  tail call void asm "add a0, a0, $0", "^cR"(i128 zeroinitializer)
+  ret void
+}
+
+define void @constraint_cR_i256() nounwind {
+; CHECK: error: couldn't allocate input reg for constraint 'cR'
+  tail call void asm "add a0, a0, $0", "^cR"(i256 zeroinitializer)
+  ret void
+}