[RISCV] Add compress patterns for Xqcilo load/store instructions #137758

svs-quic · 2025-04-29T06:18:02Z

No description provided.

llvmbot · 2025-04-29T06:18:34Z

@llvm/pr-subscribers-mc

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/137758.diff

2 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+33)
(modified) llvm/test/MC/RISCV/xqcilo-valid.s (+80-26)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 52bd893c881e8..9e46da8203baa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1323,3 +1323,36 @@ def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
 
 let Predicates = [HasVendorXqciint, IsRV32] in
 def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;
+
+
+//===----------------------------------------------------------------------===/i
+// Compress Instruction tablegen backend.
+//===----------------------------------------------------------------------===//
+
+let isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32] in {
+def : CompressPat<(QC_E_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
+                  (C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(QC_E_LW GPRNoX0:$rd, SPMem:$rs1,  uimm8_lsb00:$imm),
+                  (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12:$imm12),
+                  (LB GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
+                  (LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12:$imm12),
+                  (LH GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
+                  (LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12:$imm12),
+                  (LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
+
+def : CompressPat<(QC_E_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
+                  (C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(QC_E_SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
+                  (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
+                  (SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
+                  (SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
+def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
+                  (SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
+} // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32]
diff --git a/llvm/test/MC/RISCV/xqcilo-valid.s b/llvm/test/MC/RISCV/xqcilo-valid.s
index f2ced4698c88a..b1dd7f2910148 100644
--- a/llvm/test/MC/RISCV/xqcilo-valid.s
+++ b/llvm/test/MC/RISCV/xqcilo-valid.s
@@ -1,18 +1,18 @@
 # Xqcilo - Qualcomm uC Large Offset Load Store extension
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -M no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \
 # RUN:     | llvm-objdump --mattr=+experimental-xqcilo --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: qc.e.lb a1, 12(a0)
-# CHECK-ENC: encoding: [0x9f,0x55,0xc5,0x00,0x00,0x00]
-qc.e.lb x11, 12(x10)
+# CHECK-INST: qc.e.lb a1, 3000(a0)
+# CHECK-ENC: encoding: [0x9f,0x55,0x85,0x3b,0x02,0x00]
+qc.e.lb x11, 3000(x10)
 
 # CHECK-INST: qc.e.lb a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x9f,0x55,0x05,0x00,0x00,0x80]
@@ -23,9 +23,9 @@ qc.e.lb x11, -33554432(x10)
 qc.e.lb x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.lbu        a1, 12(a0)
-# CHECK-ENC: encoding: [0x9f,0x55,0xc5,0x40,0x00,0x00]
-qc.e.lbu x11, 12(x10)
+# CHECK-INST: qc.e.lbu        a1, 3000(a0)
+# CHECK-ENC: encoding: [0x9f,0x55,0x85,0x7b,0x02,0x00]
+qc.e.lbu x11, 3000(x10)
 
 # CHECK-INST: qc.e.lbu        a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x9f,0x55,0x05,0x40,0x00,0x80]
@@ -36,9 +36,9 @@ qc.e.lbu x11, -33554432(x10)
 qc.e.lbu x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.lh a1, 12(a0)
-# CHECK-ENC: encoding: [0x9f,0x55,0xc5,0x80,0x00,0x00]
-qc.e.lh x11, 12(x10)
+# CHECK-INST: qc.e.lh a1, 3000(a0)
+# CHECK-ENC: encoding: [0x9f,0x55,0x85,0xbb,0x02,0x00]
+qc.e.lh x11, 3000(x10)
 
 # CHECK-INST: qc.e.lh a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x9f,0x55,0x05,0x80,0x00,0x80]
@@ -49,9 +49,9 @@ qc.e.lh x11, -33554432(x10)
 qc.e.lh x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.lhu        a1, 12(a0)
-# CHECK-ENC: encoding: [0x9f,0x55,0xc5,0xc0,0x00,0x00]
-qc.e.lhu x11, 12(x10)
+# CHECK-INST: qc.e.lhu        a1, 3000(a0)
+# CHECK-ENC: encoding: [0x9f,0x55,0x85,0xfb,0x02,0x00]
+qc.e.lhu x11, 3000(x10)
 
 # CHECK-INST: qc.e.lhu        a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x9f,0x55,0x05,0xc0,0x00,0x80]
@@ -62,9 +62,9 @@ qc.e.lhu x11, -33554432(x10)
 qc.e.lhu x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.lw a1, 12(a0)
-# CHECK-ENC: encoding: [0x9f,0x65,0xc5,0x00,0x00,0x00]
-qc.e.lw x11, 12(x10)
+# CHECK-INST: qc.e.lw a1, 3000(a0)
+# CHECK-ENC: encoding: [0x9f,0x65,0x85,0x3b,0x02,0x00]
+qc.e.lw x11, 3000(x10)
 
 # CHECK-INST: qc.e.lw a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x9f,0x65,0x05,0x00,0x00,0x80]
@@ -75,9 +75,9 @@ qc.e.lw x11, -33554432(x10)
 qc.e.lw x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.sb a1, 12(a0)
-# CHECK-ENC: encoding: [0x1f,0x66,0xb5,0x40,0x00,0x00]
-qc.e.sb x11, 12(x10)
+# CHECK-INST: qc.e.sb a1, 3000(a0)
+# CHECK-ENC: encoding: [0x1f,0x6c,0xb5,0x7a,0x02,0x00]
+qc.e.sb x11, 3000(x10)
 
 # CHECK-INST: qc.e.sb a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x1f,0x60,0xb5,0x40,0x00,0x80]
@@ -88,9 +88,9 @@ qc.e.sb x11, -33554432(x10)
 qc.e.sb x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.sh a1, 12(a0)
-# CHECK-ENC: encoding: [0x1f,0x66,0xb5,0x80,0x00,0x00]
-qc.e.sh x11, 12(x10)
+# CHECK-INST: qc.e.sh a1, 3000(a0)
+# CHECK-ENC: encoding: [0x1f,0x6c,0xb5,0xba,0x02,0x00]
+qc.e.sh x11, 3000(x10)
 
 # CHECK-INST: qc.e.sh a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x1f,0x60,0xb5,0x80,0x00,0x80]
@@ -101,9 +101,9 @@ qc.e.sh x11, -33554432(x10)
 qc.e.sh x11, 33554431(x10)
 
 
-# CHECK-INST: qc.e.sw a1, 12(a0)
-# CHECK-ENC: encoding: [0x1f,0x66,0xb5,0xc0,0x00,0x00]
-qc.e.sw x11, 12(x10)
+# CHECK-INST: qc.e.sw a1, 3000(a0)
+# CHECK-ENC: encoding: [0x1f,0x6c,0xb5,0xfa,0x02,0x00]
+qc.e.sw x11, 3000(x10)
 
 # CHECK-INST: qc.e.sw a1, -33554432(a0)
 # CHECK-ENC: encoding: [0x1f,0x60,0xb5,0xc0,0x00,0x80]
@@ -112,3 +112,57 @@ qc.e.sw x11, -33554432(x10)
 # CHECK-INST: qc.e.sw a1, 33554431(a0)
 # CHECK-ENC: encoding: [0x9f,0x6f,0xb5,0xfe,0xff,0x7f]
 qc.e.sw x11, 33554431(x10)
+
+# Check that compressed patterns work
+
+# CHECK-INST: lb a1, 100(a0)
+# CHECK-ENC: encoding: [0x83,0x05,0x45,0x06]
+qc.e.lb x11, 100(x10)
+
+# CHECK-INST: lbu a1, 200(a0)
+# CHECK-ENC: encoding: [0x83,0x45,0x85,0x0c]
+qc.e.lbu x11, 200(x10)
+
+# CHECK-INST: lh a1, 300(a0)
+# CHECK-ENC: encoding: [0x83,0x15,0xc5,0x12]
+qc.e.lh x11, 300(x10)
+
+# CHECK-INST: lhu a1, 400(a0)
+# CHECK-ENC: encoding: [0x83,0x55,0x05,0x19]
+qc.e.lhu x11, 400(x10)
+
+# CHECK-INST: lw a1, 500(a0)
+# CHECK-ENC: encoding: [0x83,0x25,0x45,0x1f]
+qc.e.lw x11, 500(x10)
+
+# CHECK-INST: sb a1, 600(a0)
+# CHECK-ENC: encoding: [0x23,0x0c,0xb5,0x24]
+qc.e.sb x11, 600(x10)
+
+# CHECK-INST: sh a1, 700(a0)
+# CHECK-ENC: encoding: [0x23,0x1e,0xb5,0x2a]
+qc.e.sh x11, 700(x10)
+
+# CHECK-INST: sw a1, 800(a0)
+# CHECK-ENC: encoding: [0x23,0x20,0xb5,0x32]
+qc.e.sw x11, 800(x10)
+
+# CHECK-ALIAS: lw a1, 32(a0)
+# CHECK-NOALIAS: c.lw a1, 32(a0)
+# CHECK-ENC: encoding: [0x0c,0x51]
+qc.e.lw x11, 32(x10)
+
+# CHECK-ALIAS: sw a1, 124(a0)
+# CHECK-NOALIAS: c.sw a1, 124(a0)
+# CHECK-ENC: encoding: [0x6c,0xdd]
+qc.e.sw x11, 124(x10)
+
+# CHECK-ALIAS: lw ra, 64(sp)
+# CHECK-NOALIAS: c.lwsp ra, 64(sp)
+# CHECK-ENC: encoding: [0x86,0x40]
+qc.e.lw x1, 64(x2)
+
+# CHECK-ALIAS: sw a1, 252(sp)
+# CHECK-NOALIAS: c.swsp a1, 252(sp)
+# CHECK-ENC: encoding: [0xae,0xdf]
+qc.e.sw x11, 252(x2)

lenary · 2025-04-29T07:01:59Z

Nice. Do we need to adjust the emitter to prioritise the patterns with the biggest size savings or is the file ordering good enough?

svs-quic · 2025-04-29T07:08:35Z

Nice. Do we need to adjust the emitter to prioritise the patterns with the biggest size savings or is the file ordering good enough?

I looked at the compress patterns and they do no have an equivalent of the AddedComplexity that the ISEL patterns have. The compress patterns in RISCVInstrInfoC.td seem to be following the file ordering. Having said that, all the compress patterns till now have an uniform size saving of 2 bytes (AFAIK) so there wasn't a need to prefer one over the other.

lenary

LGTM.

We can come back to the compressed instruction emitter if file order is a problem.

…m#137758)

[RISCV] Add compress patterns for Xqcilo load/store instructions

38ff0bf

llvmbot added backend:RISC-V mc Machine (object) code labels Apr 29, 2025

svs-quic requested review from lenary, topperc, pgodeq and hchandel April 29, 2025 06:18

Fix aliases test

069b4f7

Merge branch 'main' into xqcilocomp

df8fac6

lenary approved these changes Apr 30, 2025

View reviewed changes

svs-quic merged commit 51c2602 into llvm:main Apr 30, 2025
11 checks passed

svs-quic deleted the xqcilocomp branch April 30, 2025 09:07

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[RISCV] Add compress patterns for Xqcilo load/store instructions (llv…

43ed11b

…m#137758)

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[RISCV] Add compress patterns for Xqcilo load/store instructions (llv…

96f934e

…m#137758)

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[RISCV] Add compress patterns for Xqcilo load/store instructions (llv…

285d2f4

…m#137758)

GeorgeARM pushed a commit to GeorgeARM/llvm-project that referenced this pull request May 7, 2025

[RISCV] Add compress patterns for Xqcilo load/store instructions (llv…

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…m#137758)

Ankur-0429 pushed a commit to Ankur-0429/llvm-project that referenced this pull request May 9, 2025

[RISCV] Add compress patterns for Xqcilo load/store instructions (llv…

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