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[RISCV] Xqccmp v0.3 #137854

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Merged
merged 4 commits into from
Jun 17, 2025
Merged

[RISCV] Xqccmp v0.3 #137854

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f156620
[RISCV] Xqccmp v0.3
lenary Apr 29, 2025
628c53b
Missed One
lenary Apr 29, 2025
a351ee4
Merge branch 'main' into pr/riscv-xqccmp-0.3
lenary Jun 16, 2025
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formatting
lenary Jun 16, 2025
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2 changes: 1 addition & 1 deletion clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -213,7 +213,7 @@
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmp 0.1 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension)
// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
// CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension)
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2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
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Expand Up @@ -442,7 +442,7 @@ The current vendor extensions supported are:
LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".

``experimental-Xqccmp``
LLVM implements `version 0.1 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.1.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.
LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.

``experimental-Xqcia``
LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.11.0>`__ by Qualcomm. These instructions are only available for riscv32.
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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -1426,7 +1426,8 @@ def HasVendorXwchc
// Qualcomm Extensions

def FeatureVendorXqccmp
: RISCVExperimentalExtension<0, 1, "Qualcomm 16-bit Push/Pop and Double Moves",
: RISCVExperimentalExtension<0, 3,
"Qualcomm 16-bit Push/Pop and Double Moves",
[FeatureStdExtZca]>;
def HasVendorXqccmp
: Predicate<"Subtarget->hasVendorXqccmp()">,
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -437,7 +437,7 @@
; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
; RV32XWCHC: .attribute 5, "rv32i2p1_zca1p0_xwchc2p2"
; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p1"
; RV32XQCCMP: .attribute 5, "rv32i2p1_zca1p0_xqccmp0p3"
; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p7"
; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3"
; RV32XQCIBI: .attribute 5, "rv32i2p1_zca1p0_xqcibi0p2"
Expand Down Expand Up @@ -683,7 +683,7 @@
; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0"
; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0"
; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0"
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p1"
; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3"

; RVI20U32: .attribute 5, "rv32i2p1"
; RVI20U64: .attribute 5, "rv64i2p1"
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6 changes: 3 additions & 3 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -695,13 +695,13 @@ TEST(ParseArchString, RejectsConflictingExtensions) {

for (StringRef Input :
{"rv32idc_xqciac0p3", "rv32i_zcd_xqciac0p3", "rv32idc_xqcicm0p2",
"rv32i_zcd_xqcicm0p2", "rv32idc_xqccmp0p1", "rv32i_zcd_xqccmp0p1"}) {
"rv32i_zcd_xqcicm0p2", "rv32idc_xqccmp0p3", "rv32i_zcd_xqccmp0p3"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
::testing::EndsWith("extension when 'd' extension is enabled"));
}

for (StringRef Input : {"rv32i_zcmp_xqccmp0p1", "rv64i_zcmp_xqccmp0p1"}) {
for (StringRef Input : {"rv32i_zcmp_xqccmp0p3", "rv64i_zcmp_xqccmp0p3"}) {
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcmp' and 'xqccmp' extensions are incompatible");
}
Expand Down Expand Up @@ -1184,7 +1184,7 @@ Experimental extensions
smctr 1.0
ssctr 1.0
svukte 0.3
xqccmp 0.1
xqccmp 0.3
xqcia 0.7
xqciac 0.3
xqcibi 0.2
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