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[RISCV] Add 2^N + 2^M expanding pattern for mul #137954

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May 10, 2025
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[RISCV] Add 2^N + 2^M expanding pattern for mul #137954

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42 changes: 27 additions & 15 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15456,6 +15456,30 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
}

// X * (2^N +/- 2^M) -> (add/sub (shl X, C1), (shl X, C2))
static SDValue expandMulToAddOrSubOfShl(SDNode *N, SelectionDAG &DAG,
uint64_t MulAmt) {
uint64_t MulAmtLowBit = MulAmt & (-MulAmt);
ISD::NodeType Op;
uint64_t ShiftAmt1;
if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
Op = ISD::SUB;
ShiftAmt1 = MulAmt + MulAmtLowBit;
} else if (isPowerOf2_64(MulAmt - MulAmtLowBit)) {
Op = ISD::ADD;
ShiftAmt1 = MulAmt - MulAmtLowBit;
} else {
return SDValue();
}
EVT VT = N->getValueType(0);
SDLoc DL(N);
SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
DAG.getConstant(Log2_64(ShiftAmt1), DL, VT));
SDValue Shift2 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
DAG.getConstant(Log2_64(MulAmtLowBit), DL, VT));
return DAG.getNode(Op, DL, VT, Shift1, Shift2);
}

// Try to expand a scalar multiply to a faster sequence.
static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
Expand Down Expand Up @@ -15589,22 +15613,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(ISD::SUB, DL, VT, Shift1, Mul359);
}
}
}

// 2^N - 2^M -> (sub (shl X, C1), (shl X, C2))
uint64_t MulAmtLowBit = MulAmt & (-MulAmt);
if (isPowerOf2_64(MulAmt + MulAmtLowBit)) {
uint64_t ShiftAmt1 = MulAmt + MulAmtLowBit;
SDLoc DL(N);
SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
DAG.getConstant(Log2_64(ShiftAmt1), DL, VT));
SDValue Shift2 =
DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
DAG.getConstant(Log2_64(MulAmtLowBit), DL, VT));
return DAG.getNode(ISD::SUB, DL, VT, Shift1, Shift2);
}

if (HasShlAdd) {
for (uint64_t Divisor : {3, 5, 9}) {
if (MulAmt % Divisor != 0)
continue;
Expand All @@ -15630,6 +15639,9 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG,
}
}

if (SDValue V = expandMulToAddOrSubOfShl(N, DAG, MulAmt))
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and is there any reason you moved this below strength reduction via division? (line 15681 ~ 15704)

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I vaguely remember there being a reason I broke the conditions in this order, but it looks like there's no test diffs resulting from this, so it's probably(?) fine.

return V;

return SDValue();
}

Expand Down
86 changes: 46 additions & 40 deletions llvm/test/CodeGen/RISCV/mul.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -502,24 +502,23 @@ define i32 @muli32_p18(i32 %a) nounwind {
;
; RV32IM-LABEL: muli32_p18:
; RV32IM: # %bb.0:
; RV32IM-NEXT: li a1, 18
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: slli a1, a0, 1
; RV32IM-NEXT: slli a0, a0, 4
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p18:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a1, 18
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: slli a1, a0, 1
; RV64I-NEXT: slli a0, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p18:
; RV64IM: # %bb.0:
; RV64IM-NEXT: li a1, 18
; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a1, a0, 1
; RV64IM-NEXT: slli a0, a0, 4
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 18
ret i32 %1
Expand Down Expand Up @@ -593,24 +592,23 @@ define i32 @muli32_p34(i32 %a) nounwind {
;
; RV32IM-LABEL: muli32_p34:
; RV32IM: # %bb.0:
; RV32IM-NEXT: li a1, 34
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: slli a1, a0, 1
; RV32IM-NEXT: slli a0, a0, 5
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p34:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a1, 34
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: slli a1, a0, 1
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p34:
; RV64IM: # %bb.0:
; RV64IM-NEXT: li a1, 34
; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a1, a0, 1
; RV64IM-NEXT: slli a0, a0, 5
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 34
ret i32 %1
Expand All @@ -624,24 +622,23 @@ define i32 @muli32_p36(i32 %a) nounwind {
;
; RV32IM-LABEL: muli32_p36:
; RV32IM: # %bb.0:
; RV32IM-NEXT: li a1, 36
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: slli a1, a0, 2
; RV32IM-NEXT: slli a0, a0, 5
; RV32IM-NEXT: add a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p36:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a1, 36
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: slli a1, a0, 2
; RV64I-NEXT: slli a0, a0, 5
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p36:
; RV64IM: # %bb.0:
; RV64IM-NEXT: li a1, 36
; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: slli a1, a0, 2
; RV64IM-NEXT: slli a0, a0, 5
; RV64IM-NEXT: addw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 36
ret i32 %1
Expand Down Expand Up @@ -886,10 +883,14 @@ define i64 @muli64_p72(i64 %a) nounwind {
; RV32IM-LABEL: muli64_p72:
; RV32IM: # %bb.0:
; RV32IM-NEXT: li a2, 72
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: mulhu a3, a0, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a0, a0, a2
; RV32IM-NEXT: slli a3, a1, 3
; RV32IM-NEXT: slli a1, a1, 6
; RV32IM-NEXT: add a1, a1, a3
; RV32IM-NEXT: slli a3, a0, 3
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: slli a0, a0, 6
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: add a0, a0, a3
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli64_p72:
Expand All @@ -899,8 +900,9 @@ define i64 @muli64_p72(i64 %a) nounwind {
;
; RV64IM-LABEL: muli64_p72:
; RV64IM: # %bb.0:
; RV64IM-NEXT: li a1, 72
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: slli a1, a0, 3
; RV64IM-NEXT: slli a0, a0, 6
; RV64IM-NEXT: add a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i64 %a, 72
ret i64 %1
Expand Down Expand Up @@ -1263,12 +1265,16 @@ define i64 @muli64_p4352(i64 %a) nounwind {
;
; RV32IM-LABEL: muli64_p4352:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a2, a1, 8
; RV32IM-NEXT: slli a1, a1, 12
; RV32IM-NEXT: add a1, a1, a2
; RV32IM-NEXT: li a2, 17
; RV32IM-NEXT: slli a2, a2, 8
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: mulhu a3, a0, a2
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a0, a0, a2
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: slli a2, a0, 8
; RV32IM-NEXT: slli a0, a0, 12
; RV32IM-NEXT: add a0, a0, a2
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli64_p4352:
Expand Down
55 changes: 33 additions & 22 deletions llvm/test/CodeGen/RISCV/rv32xtheadba.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -116,8 +116,9 @@ define i32 @addmul6(i32 %a, i32 %b) {
define i32 @addmul10(i32 %a, i32 %b) {
; RV32I-LABEL: addmul10:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 10
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a0, a0, 3
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -153,8 +154,9 @@ define i32 @addmul12(i32 %a, i32 %b) {
define i32 @addmul18(i32 %a, i32 %b) {
; RV32I-LABEL: addmul18:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 18
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 1
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -171,8 +173,9 @@ define i32 @addmul18(i32 %a, i32 %b) {
define i32 @addmul20(i32 %a, i32 %b) {
; RV32I-LABEL: addmul20:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 20
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a0, a0, 4
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -208,8 +211,9 @@ define i32 @addmul24(i32 %a, i32 %b) {
define i32 @addmul36(i32 %a, i32 %b) {
; RV32I-LABEL: addmul36:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 36
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 2
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -226,8 +230,9 @@ define i32 @addmul36(i32 %a, i32 %b) {
define i32 @addmul40(i32 %a, i32 %b) {
; RV32I-LABEL: addmul40:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 40
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 3
; RV32I-NEXT: slli a0, a0, 5
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -244,8 +249,9 @@ define i32 @addmul40(i32 %a, i32 %b) {
define i32 @addmul72(i32 %a, i32 %b) {
; RV32I-LABEL: addmul72:
; RV32I: # %bb.0:
; RV32I-NEXT: li a2, 72
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: slli a2, a0, 3
; RV32I-NEXT: slli a0, a0, 6
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -279,8 +285,9 @@ define i32 @mul96(i32 %a) {
define i32 @mul160(i32 %a) {
; RV32I-LABEL: mul160:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 160
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: slli a1, a0, 5
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul160:
Expand Down Expand Up @@ -312,8 +319,9 @@ define i32 @mul200(i32 %a) {
define i32 @mul288(i32 %a) {
; RV32I-LABEL: mul288:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 288
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: slli a1, a0, 5
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul288:
Expand All @@ -328,8 +336,9 @@ define i32 @mul288(i32 %a) {
define i32 @mul258(i32 %a) {
; RV32I-LABEL: mul258:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 258
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: slli a1, a0, 1
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul258:
Expand All @@ -344,8 +353,9 @@ define i32 @mul258(i32 %a) {
define i32 @mul260(i32 %a) {
; RV32I-LABEL: mul260:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 260
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: slli a1, a0, 2
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul260:
Expand All @@ -360,8 +370,9 @@ define i32 @mul260(i32 %a) {
define i32 @mul264(i32 %a) {
; RV32I-LABEL: mul264:
; RV32I: # %bb.0:
; RV32I-NEXT: li a1, 264
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: slli a1, a0, 3
; RV32I-NEXT: slli a0, a0, 8
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32XTHEADBA-LABEL: mul264:
Expand Down
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