[SPARC] Mark Niagara3 as VIS3-capable #138399
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Created using spr 1.3.5 [skip ci]
Created using spr 1.3.5
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@llvm/pr-subscribers-backend-sparc Author: Koakuma (koachan) ChangesFrom SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: Full diff: https://github.com/llvm/llvm-project/pull/138399.diff 1 Files Affected:
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 8b1122741b661..2083c0e763b82 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -156,7 +156,7 @@ def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
- FeatureVIS, FeatureVIS2]>;
+ FeatureVIS, FeatureVIS2, FeatureVIS3]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3]>;
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Created using spr 1.3.5
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From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm#138399
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May 6, 2025
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm#138399
IanWood1
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May 6, 2025
From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm#138399
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From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm/llvm-project#138399
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From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: > T3 SPARC core has a new 9 stage floating point pipeline and added Fused > Multiply-Add (FMADD) instruction and VIS 3.0 Instructions compared to > UltraSPARC T2/T2+. Reviewers: rorth, s-barannikov, brad0 Reviewed By: s-barannikov Pull Request: llvm#138399
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From SPARC T3 Supplement to the UltraSPARC Architecture 2007 Specification: