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[AMDGPU][True16][CodeGen] update more GFX11Plus codegen test with true16 mode #138600

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Merged
merged 1 commit into from
May 12, 2025
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[AMDGPU][True16][CodeGen] update more GFX11Plus codegen test with true16 mode #138600

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3,697 changes: 2,124 additions & 1,573 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.576bit.ll
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4,017 changes: 2,300 additions & 1,717 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.640bit.ll
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4,343 changes: 2,480 additions & 1,863 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.704bit.ll
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4,663 changes: 2,656 additions & 2,007 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.768bit.ll
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4,989 changes: 2,836 additions & 2,153 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.832bit.ll
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5,309 changes: 3,012 additions & 2,297 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.896bit.ll
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5,635 changes: 3,192 additions & 2,443 deletions llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.960bit.ll
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3,581 changes: 2,391 additions & 1,190 deletions llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
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3,405 changes: 2,280 additions & 1,125 deletions llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
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3,405 changes: 2,280 additions & 1,125 deletions llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
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7,121 changes: 4,768 additions & 2,353 deletions llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
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8,005 changes: 5,362 additions & 2,643 deletions llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
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8,005 changes: 5,362 additions & 2,643 deletions llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
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7,799 changes: 5,222 additions & 2,577 deletions llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
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1,079 changes: 741 additions & 338 deletions llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/gfx11-twoaddr-fma.mir
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck --check-prefixes=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 %s --passes=two-address-instruction -verify-each -o - | FileCheck --check-prefixes=GFX11 %s

---
name: test_fmamk_reg_imm_f16
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7,396 changes: 4,950 additions & 2,446 deletions llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
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7,918 changes: 5,314 additions & 2,604 deletions llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
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7,918 changes: 5,314 additions & 2,604 deletions llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
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7,756 changes: 5,196 additions & 2,560 deletions llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
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185 changes: 128 additions & 57 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.waitcnt.out.order.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1150 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1150,GFX1150-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX1150,GFX1150-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s

define amdgpu_ps <3 x float> @gather_sample(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, <8 x i32> inreg %rsrc2, <4 x i32> inreg %samp2, float %s, float %t) {
; GFX11-LABEL: gather_sample:
Expand Down Expand Up @@ -80,35 +83,69 @@ define amdgpu_ps <3 x float> @sample_gather(<8 x i32> inreg %rsrc, <4 x i32> inr
}

define amdgpu_ps <3 x float> @sample_load(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, <8 x i32> inreg %rsrc2, i16 %s.16, i16 %t.16, i16 %fragid) {
; GFX11-LABEL: sample_load:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
; GFX11-TRUE16-LABEL: sample_load:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1150-LABEL: sample_load:
; GFX1150: ; %bb.0:
; GFX1150-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX1150-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: ; return to shader part epilog
; GFX11-FAKE16-LABEL: sample_load:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: sample_load:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
; GFX1150-TRUE16-LABEL: sample_load:
; GFX1150-TRUE16: ; %bb.0:
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1150-FAKE16-LABEL: sample_load:
; GFX1150-FAKE16: ; %bb.0:
; GFX1150-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: sample_load:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: sample_load:
; GFX12-FAKE16: ; %bb.0:
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX12-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: ; return to shader part epilog

%w = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float 0.000000e+00, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i16 %s.16, i16 %t.16, i16 %fragid, <8 x i32> %rsrc2, i32 0, i32 0)
Expand All @@ -122,35 +159,69 @@ define amdgpu_ps <3 x float> @sample_load(<8 x i32> inreg %rsrc, <4 x i32> inreg
}

define amdgpu_ps <3 x float> @load_sample(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, <8 x i32> inreg %rsrc2, i16 %s.16, i16 %t.16, i16 %fragid) {
; GFX11-LABEL: load_sample:
; GFX11: ; %bb.0:
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: ; return to shader part epilog
; GFX11-TRUE16-LABEL: load_sample:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX11-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1150-LABEL: load_sample:
; GFX1150: ; %bb.0:
; GFX1150-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX1150-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-NEXT: s_waitcnt vmcnt(0)
; GFX1150-NEXT: ; return to shader part epilog
; GFX11-FAKE16-LABEL: load_sample:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX11-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-LABEL: load_sample:
; GFX12: ; %bb.0:
; GFX12-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: ; return to shader part epilog
; GFX1150-TRUE16-LABEL: load_sample:
; GFX1150-TRUE16: ; %bb.0:
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-TRUE16-NEXT: image_msaa_load v[0:3], v[2:3], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1150-FAKE16-LABEL: load_sample:
; GFX1150-FAKE16: ; %bb.0:
; GFX1150-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX1150-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX1150-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX1150-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX1150-FAKE16-NEXT: ; return to shader part epilog
;
; GFX12-TRUE16-LABEL: load_sample:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, 0
; GFX12-TRUE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: ; return to shader part epilog
;
; GFX12-FAKE16-LABEL: load_sample:
; GFX12-FAKE16: ; %bb.0:
; GFX12-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, 0
; GFX12-FAKE16-NEXT: image_msaa_load v[0:3], [v0, v2], s[12:19] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: image_sample_lz v2, [v4, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: ; return to shader part epilog

%v = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32(i32 1, i16 %s.16, i16 %t.16, i16 %fragid, <8 x i32> %rsrc2, i32 0, i32 0)
%w = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 15, float 0.000000e+00, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
Expand Down
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