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[RISCV][Peephole] Checking regclass compatibility in VMV #138844

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Merged
merged 7 commits into from
May 12, 2025
Merged

[RISCV][Peephole] Checking regclass compatibility in VMV #138844

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fbf99ce
precommit
BeMg May 7, 2025
b4c5590
[RISCV][Peephole] Checking regclass compatibility in VMV
BeMg May 7, 2025
2bd6fc4
!fixup reduce the testcase and move into vmv.v.v-peephole.mir
BeMg May 8, 2025
921cedd
!fixup Use constrainRegClass
BeMg May 9, 2025
04b2d43
!fixup reduce testcase
BeMg May 9, 2025
7bf35ca
Update llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
BeMg May 9, 2025
dc272f1
!fixup refine testcase
BeMg May 9, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -583,6 +583,8 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
}

MRI->constrainRegClass(MI.getOperand(2).getReg(),
MRI->getRegClass(MI.getOperand(0).getReg()));
MRI->replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
MRI->clearKillFlags(MI.getOperand(2).getReg());
MI.eraseFromParent();
Expand Down Expand Up @@ -653,6 +655,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
Policy |= RISCVVType::TAIL_AGNOSTIC;
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);

MRI->constrainRegClass(Src->getOperand(0).getReg(),
MRI->getRegClass(MI.getOperand(0).getReg()));
MRI->replaceRegWith(MI.getOperand(0).getReg(), Src->getOperand(0).getReg());
MI.eraseFromParent();

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30 changes: 30 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
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Expand Up @@ -105,3 +105,33 @@ body: |
%3:vr = COPY %0
...
---
name: diff_regclass
body: |
bb.0.entry:
liveins: $v8
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If you replace %4:vmv0 with $noreg then I think you can drop the livein

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ditto

; CHECK-LABEL: name: diff_regclass
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
; CHECK-NEXT: [[PseudoVADD_VV_M1_MASK:%[0-9]+]]:vrnov0 = PseudoVADD_VV_M1_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */
%0:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
%1:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %0, 0, 5 /* e32 */, 0 /* tu, mu */
%2:vmv0 = COPY $v8
%3:vrnov0 = PseudoVADD_VV_M1_MASK %1, $noreg, $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
...
---
name: diff_regclass_passthru
body: |
bb.0.entry:
liveins: $v8
; CHECK-LABEL: name: diff_regclass_passthru
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 $noreg, 0, 0, 5 /* e32 */, 1 /* ta, mu */
; CHECK-NEXT: [[COPY:%[0-9]+]]:vmv0 = COPY $v8
; CHECK-NEXT: [[PseudoVLSE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLSE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], $noreg, $noreg, [[COPY]], 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
%2:vr = PseudoVMV_V_I_MF2 $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */
%3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
%7:vmv0 = COPY $v8
%6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
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