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[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE #139214

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Merged
merged 1 commit into from
May 9, 2025
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[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE #139214

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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1264,8 +1264,8 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
else {
// The case when there is no scavenged register needs special handling.

// Pick s11 because it doesn't make a difference.
TmpGPR = RISCV::X27;
// Pick s11(or s1 for rve) because it doesn't make a difference.
TmpGPR = STI.hasStdExtE() ? RISCV::X9 : RISCV::X27;

int FrameIndex = RVFI->getBranchRelaxationScratchFrameIndex();
if (FrameIndex == -1)
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