[NFC][TableGen] Use StringRef in X86RecognizableInstr #139648
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-backend-x86 Author: Rahul Joshi (jurahul) Changes
Full diff: https://github.com/llvm/llvm-project/pull/139648.diff 2 Files Affected:
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 402fc93703228..9e49ac2ad8377 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -440,8 +440,7 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
void RecognizableInstr::handleOperand(
bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
unsigned numPhysicalOperands, const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)(const std::string &,
- uint8_t OpSize)) {
+ OperandEncoding (*encodingFromString)(StringRef, uint8_t OpSize)) {
if (optional) {
if (physicalOperandIndex >= numPhysicalOperands)
return;
@@ -458,12 +457,12 @@ void RecognizableInstr::handleOperand(
StringRef typeName = (*Operands)[operandIndex].Rec->getName();
- OperandEncoding encoding = encodingFromString(typeName.str(), OpSize);
+ OperandEncoding encoding = encodingFromString(typeName, OpSize);
// Adjust the encoding type for an operand based on the instruction.
adjustOperandEncoding(encoding);
Spec->operands[operandIndex].encoding = encoding;
Spec->operands[operandIndex].type =
- typeFromString(typeName.str(), HasREX_W, OpSize);
+ typeFromString(typeName, HasREX_W, OpSize);
++operandIndex;
++physicalOperandIndex;
@@ -1020,11 +1019,11 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
#undef MAP
}
-#define TYPE(str, type) \
- if (s == str) \
- return type;
-OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool hasREX_W, uint8_t OpSize) {
+#define TYPE(Expected, Type) \
+ if (Str == Expected) \
+ return Type;
+OperandType RecognizableInstr::typeFromString(StringRef Str, bool hasREX_W,
+ uint8_t OpSize) {
if (hasREX_W) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
@@ -1163,17 +1162,16 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("BNDR", TYPE_BNDR)
TYPE("TILE", TYPE_TMM)
TYPE("TILEPair", TYPE_TMM_PAIR)
- errs() << "Unhandled type string " << s << "\n";
+ errs() << "Unhandled type string " << Str << "\n";
llvm_unreachable("Unhandled type string");
}
#undef TYPE
-#define ENCODING(str, encoding) \
- if (s == str) \
- return encoding;
-OperandEncoding
-RecognizableInstr::immediateEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+#define ENCODING(Expected, Encoding) \
+ if (Str == Expected) \
+ return Encoding;
+OperandEncoding RecognizableInstr::immediateEncodingFromString(StringRef Str,
+ uint8_t OpSize) {
if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
@@ -1208,13 +1206,12 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
ENCODING("VR256X", ENCODING_IB)
ENCODING("VR512", ENCODING_IB)
ENCODING("TILE", ENCODING_IB)
- errs() << "Unhandled immediate encoding " << s << "\n";
+ errs() << "Unhandled immediate encoding " << Str << "\n";
llvm_unreachable("Unhandled immediate encoding");
}
OperandEncoding
-RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::rmRegisterEncodingFromString(StringRef Str, uint8_t OpSize) {
ENCODING("RST", ENCODING_FP)
ENCODING("RSTi", ENCODING_FP)
ENCODING("GR16", ENCODING_RM)
@@ -1245,13 +1242,12 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
ENCODING("BNDR", ENCODING_RM)
ENCODING("TILE", ENCODING_RM)
ENCODING("TILEPair", ENCODING_RM)
- errs() << "Unhandled R/M register encoding " << s << "\n";
+ errs() << "Unhandled R/M register encoding " << Str << "\n";
llvm_unreachable("Unhandled R/M register encoding");
}
OperandEncoding
-RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::roRegisterEncodingFromString(StringRef Str, uint8_t OpSize) {
ENCODING("GR16", ENCODING_REG)
ENCODING("GR16orGR32orGR64", ENCODING_REG)
ENCODING("GR32", ENCODING_REG)
@@ -1295,12 +1291,12 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
ENCODING("BNDR", ENCODING_REG)
ENCODING("TILE", ENCODING_REG)
ENCODING("TILEPair", ENCODING_REG)
- errs() << "Unhandled reg/opcode register encoding " << s << "\n";
+ errs() << "Unhandled reg/opcode register encoding " << Str << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding");
}
OperandEncoding
-RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
+RecognizableInstr::vvvvRegisterEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("GR8", ENCODING_VVVV)
ENCODING("GR16", ENCODING_VVVV)
@@ -1326,12 +1322,12 @@ RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
ENCODING("VK64", ENCODING_VVVV)
ENCODING("TILE", ENCODING_VVVV)
ENCODING("TILEPair", ENCODING_VVVV)
- errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
+ errs() << "Unhandled VEX.vvvv register encoding " << Str << "\n";
llvm_unreachable("Unhandled VEX.vvvv register encoding");
}
OperandEncoding
-RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
+RecognizableInstr::writemaskRegisterEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("VK1WM", ENCODING_WRITEMASK)
ENCODING("VK2WM", ENCODING_WRITEMASK)
@@ -1340,13 +1336,12 @@ RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
ENCODING("VK16WM", ENCODING_WRITEMASK)
ENCODING("VK32WM", ENCODING_WRITEMASK)
ENCODING("VK64WM", ENCODING_WRITEMASK)
- errs() << "Unhandled mask register encoding " << s << "\n";
+ errs() << "Unhandled mask register encoding " << Str << "\n";
llvm_unreachable("Unhandled mask register encoding");
}
-OperandEncoding
-RecognizableInstr::memoryEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+OperandEncoding RecognizableInstr::memoryEncodingFromString(StringRef Str,
+ uint8_t OpSize) {
ENCODING("i16mem", ENCODING_RM)
ENCODING("i32mem", ENCODING_RM)
ENCODING("i64mem", ENCODING_RM)
@@ -1384,13 +1379,12 @@ RecognizableInstr::memoryEncodingFromString(const std::string &s,
ENCODING("vy64xmem", ENCODING_VSIB)
ENCODING("vz32mem", ENCODING_VSIB)
ENCODING("vz64mem", ENCODING_VSIB)
- errs() << "Unhandled memory encoding " << s << "\n";
+ errs() << "Unhandled memory encoding " << Str << "\n";
llvm_unreachable("Unhandled memory encoding");
}
OperandEncoding
-RecognizableInstr::relocationEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::relocationEncodingFromString(StringRef Str, uint8_t OpSize) {
if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
@@ -1434,19 +1428,19 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
ENCODING("dstidx16", ENCODING_DI)
ENCODING("dstidx32", ENCODING_DI)
ENCODING("dstidx64", ENCODING_DI)
- errs() << "Unhandled relocation encoding " << s << "\n";
+ errs() << "Unhandled relocation encoding " << Str << "\n";
llvm_unreachable("Unhandled relocation encoding");
}
OperandEncoding
-RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
+RecognizableInstr::opcodeModifierEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("GR32", ENCODING_Rv)
ENCODING("GR64", ENCODING_RO)
ENCODING("GR16", ENCODING_Rv)
ENCODING("GR8", ENCODING_RB)
ENCODING("ccode", ENCODING_CC)
- errs() << "Unhandled opcode modifier encoding " << s << "\n";
+ errs() << "Unhandled opcode modifier encoding " << Str << "\n";
llvm_unreachable("Unhandled opcode modifier encoding");
}
#undef ENCODING
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index eb2cee7bbbf87..8f28aedb235b8 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -281,7 +281,7 @@ class RecognizableInstr : public RecognizableInstrBase {
/// If register size does not match OpSize, then
/// register sizes keep their size.
/// @return - The operand's type.
- static OperandType typeFromString(const std::string &s, bool hasREX_W,
+ static OperandType typeFromString(StringRef Str, bool hasREX_W,
uint8_t OpSize);
/// immediateEncodingFromString - Translates an immediate encoding from the
@@ -292,28 +292,28 @@ class RecognizableInstr : public RecognizableInstrBase {
/// @param OpSize - Indicates whether this is an OpSize16 instruction.
/// If it is not, then 16-bit immediate operands stay 16-bit.
/// @return - The operand's encoding.
- static OperandEncoding immediateEncodingFromString(const std::string &s,
+ static OperandEncoding immediateEncodingFromString(StringRef Str,
uint8_t OpSize);
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
/// handles operands that are in the REG field of the ModR/M byte.
- static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding rmRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
/// handles operands that are in the REG field of the ModR/M byte.
- static OperandEncoding roRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding roRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding memoryEncodingFromString(const std::string &s,
+ static OperandEncoding memoryEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding relocationEncodingFromString(const std::string &s,
+ static OperandEncoding relocationEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
+ static OperandEncoding opcodeModifierEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding vvvvRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding
- writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize);
+ static OperandEncoding writemaskRegisterEncodingFromString(StringRef Str,
+ uint8_t OpSize);
/// Adjust the encoding type for an operand based on the instruction.
void adjustOperandEncoding(OperandEncoding &encoding);
@@ -336,12 +336,10 @@ class RecognizableInstr : public RecognizableInstrBase {
/// @param operandMapping - The operand mapping, which has an entry for
/// each operand that indicates whether it is a
/// duplicate, and of what.
- void handleOperand(bool optional, unsigned &operandIndex,
- unsigned &physicalOperandIndex,
- unsigned numPhysicalOperands,
- const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)(const std::string &,
- uint8_t OpSize));
+ void handleOperand(
+ bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
+ unsigned numPhysicalOperands, const unsigned *operandMapping,
+ OperandEncoding (*encodingFromString)(StringRef s, uint8_t OpSize));
/// emitInstructionSpecifier - Loads the instruction specifier for the current
/// instruction into a DisassemblerTables.
|
|
@llvm/pr-subscribers-tablegen Author: Rahul Joshi (jurahul) Changes
Full diff: https://github.com/llvm/llvm-project/pull/139648.diff 2 Files Affected:
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 402fc93703228..9e49ac2ad8377 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -440,8 +440,7 @@ void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
void RecognizableInstr::handleOperand(
bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
unsigned numPhysicalOperands, const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)(const std::string &,
- uint8_t OpSize)) {
+ OperandEncoding (*encodingFromString)(StringRef, uint8_t OpSize)) {
if (optional) {
if (physicalOperandIndex >= numPhysicalOperands)
return;
@@ -458,12 +457,12 @@ void RecognizableInstr::handleOperand(
StringRef typeName = (*Operands)[operandIndex].Rec->getName();
- OperandEncoding encoding = encodingFromString(typeName.str(), OpSize);
+ OperandEncoding encoding = encodingFromString(typeName, OpSize);
// Adjust the encoding type for an operand based on the instruction.
adjustOperandEncoding(encoding);
Spec->operands[operandIndex].encoding = encoding;
Spec->operands[operandIndex].type =
- typeFromString(typeName.str(), HasREX_W, OpSize);
+ typeFromString(typeName, HasREX_W, OpSize);
++operandIndex;
++physicalOperandIndex;
@@ -1020,11 +1019,11 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
#undef MAP
}
-#define TYPE(str, type) \
- if (s == str) \
- return type;
-OperandType RecognizableInstr::typeFromString(const std::string &s,
- bool hasREX_W, uint8_t OpSize) {
+#define TYPE(Expected, Type) \
+ if (Str == Expected) \
+ return Type;
+OperandType RecognizableInstr::typeFromString(StringRef Str, bool hasREX_W,
+ uint8_t OpSize) {
if (hasREX_W) {
// For instructions with a REX_W prefix, a declared 32-bit register encoding
// is special.
@@ -1163,17 +1162,16 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("BNDR", TYPE_BNDR)
TYPE("TILE", TYPE_TMM)
TYPE("TILEPair", TYPE_TMM_PAIR)
- errs() << "Unhandled type string " << s << "\n";
+ errs() << "Unhandled type string " << Str << "\n";
llvm_unreachable("Unhandled type string");
}
#undef TYPE
-#define ENCODING(str, encoding) \
- if (s == str) \
- return encoding;
-OperandEncoding
-RecognizableInstr::immediateEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+#define ENCODING(Expected, Encoding) \
+ if (Str == Expected) \
+ return Encoding;
+OperandEncoding RecognizableInstr::immediateEncodingFromString(StringRef Str,
+ uint8_t OpSize) {
if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
@@ -1208,13 +1206,12 @@ RecognizableInstr::immediateEncodingFromString(const std::string &s,
ENCODING("VR256X", ENCODING_IB)
ENCODING("VR512", ENCODING_IB)
ENCODING("TILE", ENCODING_IB)
- errs() << "Unhandled immediate encoding " << s << "\n";
+ errs() << "Unhandled immediate encoding " << Str << "\n";
llvm_unreachable("Unhandled immediate encoding");
}
OperandEncoding
-RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::rmRegisterEncodingFromString(StringRef Str, uint8_t OpSize) {
ENCODING("RST", ENCODING_FP)
ENCODING("RSTi", ENCODING_FP)
ENCODING("GR16", ENCODING_RM)
@@ -1245,13 +1242,12 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
ENCODING("BNDR", ENCODING_RM)
ENCODING("TILE", ENCODING_RM)
ENCODING("TILEPair", ENCODING_RM)
- errs() << "Unhandled R/M register encoding " << s << "\n";
+ errs() << "Unhandled R/M register encoding " << Str << "\n";
llvm_unreachable("Unhandled R/M register encoding");
}
OperandEncoding
-RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::roRegisterEncodingFromString(StringRef Str, uint8_t OpSize) {
ENCODING("GR16", ENCODING_REG)
ENCODING("GR16orGR32orGR64", ENCODING_REG)
ENCODING("GR32", ENCODING_REG)
@@ -1295,12 +1291,12 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
ENCODING("BNDR", ENCODING_REG)
ENCODING("TILE", ENCODING_REG)
ENCODING("TILEPair", ENCODING_REG)
- errs() << "Unhandled reg/opcode register encoding " << s << "\n";
+ errs() << "Unhandled reg/opcode register encoding " << Str << "\n";
llvm_unreachable("Unhandled reg/opcode register encoding");
}
OperandEncoding
-RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
+RecognizableInstr::vvvvRegisterEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("GR8", ENCODING_VVVV)
ENCODING("GR16", ENCODING_VVVV)
@@ -1326,12 +1322,12 @@ RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
ENCODING("VK64", ENCODING_VVVV)
ENCODING("TILE", ENCODING_VVVV)
ENCODING("TILEPair", ENCODING_VVVV)
- errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
+ errs() << "Unhandled VEX.vvvv register encoding " << Str << "\n";
llvm_unreachable("Unhandled VEX.vvvv register encoding");
}
OperandEncoding
-RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
+RecognizableInstr::writemaskRegisterEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("VK1WM", ENCODING_WRITEMASK)
ENCODING("VK2WM", ENCODING_WRITEMASK)
@@ -1340,13 +1336,12 @@ RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
ENCODING("VK16WM", ENCODING_WRITEMASK)
ENCODING("VK32WM", ENCODING_WRITEMASK)
ENCODING("VK64WM", ENCODING_WRITEMASK)
- errs() << "Unhandled mask register encoding " << s << "\n";
+ errs() << "Unhandled mask register encoding " << Str << "\n";
llvm_unreachable("Unhandled mask register encoding");
}
-OperandEncoding
-RecognizableInstr::memoryEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+OperandEncoding RecognizableInstr::memoryEncodingFromString(StringRef Str,
+ uint8_t OpSize) {
ENCODING("i16mem", ENCODING_RM)
ENCODING("i32mem", ENCODING_RM)
ENCODING("i64mem", ENCODING_RM)
@@ -1384,13 +1379,12 @@ RecognizableInstr::memoryEncodingFromString(const std::string &s,
ENCODING("vy64xmem", ENCODING_VSIB)
ENCODING("vz32mem", ENCODING_VSIB)
ENCODING("vz64mem", ENCODING_VSIB)
- errs() << "Unhandled memory encoding " << s << "\n";
+ errs() << "Unhandled memory encoding " << Str << "\n";
llvm_unreachable("Unhandled memory encoding");
}
OperandEncoding
-RecognizableInstr::relocationEncodingFromString(const std::string &s,
- uint8_t OpSize) {
+RecognizableInstr::relocationEncodingFromString(StringRef Str, uint8_t OpSize) {
if (OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special.
@@ -1434,19 +1428,19 @@ RecognizableInstr::relocationEncodingFromString(const std::string &s,
ENCODING("dstidx16", ENCODING_DI)
ENCODING("dstidx32", ENCODING_DI)
ENCODING("dstidx64", ENCODING_DI)
- errs() << "Unhandled relocation encoding " << s << "\n";
+ errs() << "Unhandled relocation encoding " << Str << "\n";
llvm_unreachable("Unhandled relocation encoding");
}
OperandEncoding
-RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
+RecognizableInstr::opcodeModifierEncodingFromString(StringRef Str,
uint8_t OpSize) {
ENCODING("GR32", ENCODING_Rv)
ENCODING("GR64", ENCODING_RO)
ENCODING("GR16", ENCODING_Rv)
ENCODING("GR8", ENCODING_RB)
ENCODING("ccode", ENCODING_CC)
- errs() << "Unhandled opcode modifier encoding " << s << "\n";
+ errs() << "Unhandled opcode modifier encoding " << Str << "\n";
llvm_unreachable("Unhandled opcode modifier encoding");
}
#undef ENCODING
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index eb2cee7bbbf87..8f28aedb235b8 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -281,7 +281,7 @@ class RecognizableInstr : public RecognizableInstrBase {
/// If register size does not match OpSize, then
/// register sizes keep their size.
/// @return - The operand's type.
- static OperandType typeFromString(const std::string &s, bool hasREX_W,
+ static OperandType typeFromString(StringRef Str, bool hasREX_W,
uint8_t OpSize);
/// immediateEncodingFromString - Translates an immediate encoding from the
@@ -292,28 +292,28 @@ class RecognizableInstr : public RecognizableInstrBase {
/// @param OpSize - Indicates whether this is an OpSize16 instruction.
/// If it is not, then 16-bit immediate operands stay 16-bit.
/// @return - The operand's encoding.
- static OperandEncoding immediateEncodingFromString(const std::string &s,
+ static OperandEncoding immediateEncodingFromString(StringRef Str,
uint8_t OpSize);
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
/// handles operands that are in the REG field of the ModR/M byte.
- static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding rmRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
/// handles operands that are in the REG field of the ModR/M byte.
- static OperandEncoding roRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding roRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding memoryEncodingFromString(const std::string &s,
+ static OperandEncoding memoryEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding relocationEncodingFromString(const std::string &s,
+ static OperandEncoding relocationEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
+ static OperandEncoding opcodeModifierEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
+ static OperandEncoding vvvvRegisterEncodingFromString(StringRef Str,
uint8_t OpSize);
- static OperandEncoding
- writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize);
+ static OperandEncoding writemaskRegisterEncodingFromString(StringRef Str,
+ uint8_t OpSize);
/// Adjust the encoding type for an operand based on the instruction.
void adjustOperandEncoding(OperandEncoding &encoding);
@@ -336,12 +336,10 @@ class RecognizableInstr : public RecognizableInstrBase {
/// @param operandMapping - The operand mapping, which has an entry for
/// each operand that indicates whether it is a
/// duplicate, and of what.
- void handleOperand(bool optional, unsigned &operandIndex,
- unsigned &physicalOperandIndex,
- unsigned numPhysicalOperands,
- const unsigned *operandMapping,
- OperandEncoding (*encodingFromString)(const std::string &,
- uint8_t OpSize));
+ void handleOperand(
+ bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex,
+ unsigned numPhysicalOperands, const unsigned *operandMapping,
+ OperandEncoding (*encodingFromString)(StringRef s, uint8_t OpSize));
/// emitInstructionSpecifier - Loads the instruction specifier for the current
/// instruction into a DisassemblerTables.
|
wangpc-pp
reviewed
May 13, 2025
jurahul
force-pushed
the
tablegen_use_stringref_X86RecognizableInstr
branch
from
f77eda8 to
4b036ca
Compare
wangpc-pp
reviewed
May 14, 2025
jurahul
force-pushed
the
tablegen_use_stringref_X86RecognizableInstr
branch
from
4b036ca to
833d836
Compare
KanRobert
reviewed
May 14, 2025
- Use `StringRef` instead of `std::string` in several functions. - Fix some variable names to conform to LLVM coding standard.
jurahul
force-pushed
the
tablegen_use_stringref_X86RecognizableInstr
branch
from
833d836 to
46edb8d
Compare
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/162/builds/22374 Here is the relevant piece of the build log for the reference |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
StringRefinstead ofstd::stringin several functions.handleOperandargument.