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[RISCV] Add isel patterns for generating Xqcibi branch instructions #139872

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Merged
merged 4 commits into from
May 16, 2025
Merged

[RISCV] Add isel patterns for generating Xqcibi branch instructions #139872

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3da539c
[RISCV] Add isel patterns for generating Xqcibi branch instructions
svs-quic May 14, 2025
2548040
Use cast and add INT64_MAX check
svs-quic May 15, 2025
79780d1
Clang format
svs-quic May 15, 2025
6120e65
Merge branch 'main' into xqcibi_patterns
svs-quic May 16, 2025
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23 changes: 23 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2400,6 +2400,8 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,

if (auto *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
int64_t C = RHSC->getSExtValue();
const RISCVSubtarget &Subtarget =
DAG.getMachineFunction().getSubtarget<RISCVSubtarget>();
switch (CC) {
default: break;
case ISD::SETGT:
Expand All @@ -2409,6 +2411,13 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
CC = ISD::SETGE;
return;
}
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1)) {
// We have a branch immediate instruction for SETGE but not SETGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
CC = ISD::SETGE;
return;
}
break;
case ISD::SETLT:
// Convert X < 1 to 0 >= X.
Expand All @@ -2419,6 +2428,16 @@ static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS,
return;
}
break;
case ISD::SETUGT:
if (Subtarget.hasVendorXqcibi() && C != INT64_MAX && isInt<16>(C + 1) &&
C != -1) {
// We have a branch immediate instruction for SETUGE but not SETUGT.
// Convert X > C to X >= C + 1, if (C + 1) is a 16-bit signed immediate.
RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType());
CC = ISD::SETUGE;
return;
}
break;
}
}

Expand Down Expand Up @@ -21298,6 +21317,10 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
return emitReadCounterWidePseudo(MI, BB);
case RISCV::Select_GPR_Using_CC_GPR:
case RISCV::Select_GPR_Using_CC_Imm:
case RISCV::Select_GPR_Using_CC_Simm5NonZero:
case RISCV::Select_GPR_Using_CC_Uimm5NonZero:
case RISCV::Select_GPR_Using_CC_Simm16NonZero:
case RISCV::Select_GPR_Using_CC_Uimm16NonZero:
case RISCV::Select_FPR16_Using_CC_GPR:
case RISCV::Select_FPR16INX_Using_CC_GPR:
case RISCV::Select_FPR32_Using_CC_GPR:
Expand Down
96 changes: 96 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -977,6 +977,30 @@ static RISCVCC::CondCode getCondFromBranchOpc(unsigned Opc) {
return RISCVCC::COND_CV_BEQIMM;
case RISCV::CV_BNEIMM:
return RISCVCC::COND_CV_BNEIMM;
case RISCV::QC_BEQI:
return RISCVCC::COND_QC_BEQI;
case RISCV::QC_E_BEQI:
return RISCVCC::COND_QC_E_BEQI;
case RISCV::QC_BNEI:
return RISCVCC::COND_QC_BNEI;
case RISCV::QC_E_BNEI:
return RISCVCC::COND_QC_E_BNEI;
case RISCV::QC_BLTI:
return RISCVCC::COND_QC_BLTI;
case RISCV::QC_E_BLTI:
return RISCVCC::COND_QC_E_BLTI;
case RISCV::QC_BGEI:
return RISCVCC::COND_QC_BGEI;
case RISCV::QC_E_BGEI:
return RISCVCC::COND_QC_E_BGEI;
case RISCV::QC_BLTUI:
return RISCVCC::COND_QC_BLTUI;
case RISCV::QC_E_BLTUI:
return RISCVCC::COND_QC_E_BLTUI;
case RISCV::QC_BGEUI:
return RISCVCC::COND_QC_BGEUI;
case RISCV::QC_E_BGEUI:
return RISCVCC::COND_QC_E_BGEUI;
}
}

Expand Down Expand Up @@ -1034,6 +1058,30 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) {
return RISCV::CV_BEQIMM;
case RISCVCC::COND_CV_BNEIMM:
return RISCV::CV_BNEIMM;
case RISCVCC::COND_QC_BEQI:
return RISCV::QC_BEQI;
case RISCVCC::COND_QC_E_BEQI:
return RISCV::QC_E_BEQI;
case RISCVCC::COND_QC_BNEI:
return RISCV::QC_BNEI;
case RISCVCC::COND_QC_E_BNEI:
return RISCV::QC_E_BNEI;
case RISCVCC::COND_QC_BLTI:
return RISCV::QC_BLTI;
case RISCVCC::COND_QC_E_BLTI:
return RISCV::QC_E_BLTI;
case RISCVCC::COND_QC_BGEI:
return RISCV::QC_BGEI;
case RISCVCC::COND_QC_E_BGEI:
return RISCV::QC_E_BGEI;
case RISCVCC::COND_QC_BLTUI:
return RISCV::QC_BLTUI;
case RISCVCC::COND_QC_E_BLTUI:
return RISCV::QC_E_BLTUI;
case RISCVCC::COND_QC_BGEUI:
return RISCV::QC_BGEUI;
case RISCVCC::COND_QC_E_BGEUI:
return RISCV::QC_E_BGEUI;
}
}

Expand Down Expand Up @@ -1061,6 +1109,30 @@ RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) {
return RISCVCC::COND_CV_BNEIMM;
case RISCVCC::COND_CV_BNEIMM:
return RISCVCC::COND_CV_BEQIMM;
case RISCVCC::COND_QC_BEQI:
return RISCVCC::COND_QC_BNEI;
case RISCVCC::COND_QC_E_BEQI:
return RISCVCC::COND_QC_E_BNEI;
case RISCVCC::COND_QC_BNEI:
return RISCVCC::COND_QC_BEQI;
case RISCVCC::COND_QC_E_BNEI:
return RISCVCC::COND_QC_E_BEQI;
case RISCVCC::COND_QC_BLTI:
return RISCVCC::COND_QC_BGEI;
case RISCVCC::COND_QC_E_BLTI:
return RISCVCC::COND_QC_E_BGEI;
case RISCVCC::COND_QC_BGEI:
return RISCVCC::COND_QC_BLTI;
case RISCVCC::COND_QC_E_BGEI:
return RISCVCC::COND_QC_E_BLTI;
case RISCVCC::COND_QC_BLTUI:
return RISCVCC::COND_QC_BGEUI;
case RISCVCC::COND_QC_E_BLTUI:
return RISCVCC::COND_QC_E_BGEUI;
case RISCVCC::COND_QC_BGEUI:
return RISCVCC::COND_QC_BLTUI;
case RISCVCC::COND_QC_E_BGEUI:
return RISCVCC::COND_QC_E_BLTUI;
}
}

Expand Down Expand Up @@ -1436,6 +1508,18 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
case RISCV::BGEU:
case RISCV::CV_BEQIMM:
case RISCV::CV_BNEIMM:
case RISCV::QC_BEQI:
case RISCV::QC_BNEI:
case RISCV::QC_BGEI:
case RISCV::QC_BLTI:
case RISCV::QC_BLTUI:
case RISCV::QC_BGEUI:
case RISCV::QC_E_BEQI:
case RISCV::QC_E_BNEI:
case RISCV::QC_E_BGEI:
case RISCV::QC_E_BLTI:
case RISCV::QC_E_BLTUI:
case RISCV::QC_E_BGEUI:
return isIntN(13, BrOffset);
case RISCV::JAL:
case RISCV::PseudoBR:
Expand Down Expand Up @@ -2617,6 +2701,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM5_LSB0:
Ok = isShiftedUInt<4, 1>(Imm);
break;
case RISCVOp::OPERAND_UIMM5_NONZERO:
Ok = isUInt<5>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_UIMM6_LSB0:
Ok = isShiftedUInt<5, 1>(Imm);
break;
Expand Down Expand Up @@ -2644,6 +2731,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_UIMM10_LSB00_NONZERO:
Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_UIMM16_NONZERO:
Ok = isUInt<16>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_ZERO:
Ok = Imm == 0;
break;
Expand All @@ -2663,6 +2753,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_SIMM5_PLUS1:
Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
break;
case RISCVOp::OPERAND_SIMM5_NONZERO:
Ok = isInt<5>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_SIMM6_NONZERO:
Ok = Imm != 0 && isInt<6>(Imm);
break;
Expand All @@ -2675,6 +2768,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
case RISCVOp::OPERAND_SIMM12_LSB00000:
Ok = isShiftedInt<7, 5>(Imm);
break;
case RISCVOp::OPERAND_SIMM16_NONZERO:
Ok = isInt<16>(Imm) && (Imm != 0);
break;
case RISCVOp::OPERAND_SIMM20_LI:
Ok = isInt<20>(Imm);
break;
Expand Down
12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,18 @@ enum CondCode {
COND_GEU,
COND_CV_BEQIMM,
COND_CV_BNEIMM,
COND_QC_BEQI,
COND_QC_BNEI,
COND_QC_BLTI,
COND_QC_BGEI,
COND_QC_BLTUI,
COND_QC_BGEUI,
COND_QC_E_BEQI,
COND_QC_E_BNEI,
COND_QC_E_BLTI,
COND_QC_E_BGEI,
COND_QC_E_BLTUI,
COND_QC_E_BGEUI,
COND_INVALID
};

Expand Down
92 changes: 92 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
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Original file line number Diff line number Diff line change
Expand Up @@ -188,6 +188,36 @@ def AddLike: PatFrags<(ops node:$A, node:$B),
def AddShl : PatFrag<(ops node:$Ra, node:$Rb, node:$SH3),
(add node:$Ra, (shl node:$Rb, node:$SH3))>;

def IntCCtoQCRISCVCC : SDNodeXForm<riscv_selectcc, [{
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
int64_t Imm = cast<ConstantSDNode>(N->getOperand(1))->getSExtValue();
RISCVCC::CondCode BrCC;
switch (CC) {
default:
report_fatal_error("Unexpected CondCode for Xqcibi branch instructions");
case ISD::SETEQ:
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BEQI : RISCVCC::COND_QC_E_BEQI;
break;
case ISD::SETNE:
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BNEI : RISCVCC::COND_QC_E_BNEI;
break;
case ISD::SETLT:
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BLTI : RISCVCC::COND_QC_E_BLTI;
break;
case ISD::SETGE:
BrCC = isInt<5>(Imm) ? RISCVCC::COND_QC_BGEI : RISCVCC::COND_QC_E_BGEI;
break;
case ISD::SETULT:
BrCC = isUInt<5>(Imm) ? RISCVCC::COND_QC_BLTUI : RISCVCC::COND_QC_E_BLTUI;
break;
case ISD::SETUGE:
BrCC = isUInt<5>(Imm) ? RISCVCC::COND_QC_BGEUI : RISCVCC::COND_QC_E_BGEUI;
break;
}
return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
}]>;


//===----------------------------------------------------------------------===//
// Instruction Formats
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -1288,6 +1318,36 @@ class QCScaledStPat<PatFrag StoreOp, RVInst Inst>
: Pat<(StoreOp (i32 GPR:$rd), (AddShl (i32 GPRMem:$rs1), (i32 GPRNoX0:$rs2), uimm3:$shamt)),
(Inst GPR:$rd, GPRMem:$rs1, GPRNoX0:$rs2, uimm3:$shamt)>;

// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
class BcciPat<CondCode Cond, QCIBranchInst_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;

class Bcci48Pat<CondCode Cond, QCIBranchInst48_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
(Inst GPRNoX0:$rs1, InTyImm:$rs2, bare_simm13_lsb0:$imm12)>;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0, usesCustomInserter = 1 in {
def Select_GPR_Using_CC_Simm5NonZero : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, simm5nonzero:$imm5,
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
def Select_GPR_Using_CC_Uimm5NonZero : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, uimm5nonzero:$imm5,
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
def Select_GPR_Using_CC_Simm16NonZero : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, simm16nonzero:$imm16,
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
def Select_GPR_Using_CC_Uimm16NonZero : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, uimm16nonzero:$imm16,
cond_code:$cc, GPR:$truev, GPR:$falsev), []>;
}

class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
: Pat<(riscv_selectcc_frag:$cc (i32 GPR:$lhs), InTyImm:$Constant, Cond,
(i32 GPR:$truev), GPR:$falsev),
(OpNode GPR:$lhs, InTyImm:$Constant,
(IntCCtoQCRISCVCC $cc), GPR:$truev, GPR:$falsev)>;

/// Simple arithmetic operations

let Predicates = [HasVendorXqcilia, IsRV32] in {
Expand Down Expand Up @@ -1342,6 +1402,38 @@ def : PatGprNoX0GprNoX0<ushlsat, QC_SHLUSAT>;
def : PatGprNoX0GprNoX0<sshlsat, QC_SHLSAT>;
} // Predicates = [HasVendorXqcia, IsRV32]

/// Branches

let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 in {
def : BcciPat<SETEQ, QC_BEQI, simm5nonzero>;
def : BcciPat<SETNE, QC_BNEI, simm5nonzero>;
def : BcciPat<SETLT, QC_BLTI, simm5nonzero>;
def : BcciPat<SETGE, QC_BGEI, simm5nonzero>;
def : BcciPat<SETULT, QC_BLTUI, uimm5nonzero>;
def : BcciPat<SETUGE, QC_BGEUI, uimm5nonzero>;

def : Bcci48Pat<SETEQ, QC_E_BEQI, simm16nonzero>;
def : Bcci48Pat<SETNE, QC_E_BNEI, simm16nonzero>;
def : Bcci48Pat<SETLT, QC_E_BLTI, simm16nonzero>;
def : Bcci48Pat<SETGE, QC_E_BGEI, simm16nonzero>;
def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;

def : SelectQCbi<SETEQ, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
def : SelectQCbi<SETNE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
def : SelectQCbi<SETLT, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
def : SelectQCbi<SETGE, simm5nonzero, Select_GPR_Using_CC_Simm5NonZero>;
def : SelectQCbi<SETULT, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;
def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPR_Using_CC_Uimm5NonZero>;

def : SelectQCbi<SETEQ, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
def : SelectQCbi<SETNE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
def : SelectQCbi<SETLT, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
def : SelectQCbi<SETGE, simm16nonzero, Select_GPR_Using_CC_Simm16NonZero>;
def : SelectQCbi<SETULT, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPR_Using_CC_Uimm16NonZero>;
} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2

let Predicates = [HasVendorXqciint, IsRV32] in
def : Pat<(riscv_mileaveret_glue), (QC_C_MILEAVERET)>;

Expand Down
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