Skip to content

[RISCV] [NFC] Add llvm.get.rounding test #139921

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
May 19, 2025
Merged

[RISCV] [NFC] Add llvm.get.rounding test #139921

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
83 changes: 83 additions & 0 deletions llvm/test/CodeGen/RISCV/fpenv.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,85 @@ define i32 @func_01() {
ret i32 %rm
}

define i1 @test_get_rounding_sideeffect() #0 {
; RV32IF-LABEL: test_get_rounding_sideeffect:
; RV32IF: # %bb.0: # %entry
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: .cfi_def_cfa_offset 16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: .cfi_offset s0, -8
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: call fesetround
; RV32IF-NEXT: frrm a0
; RV32IF-NEXT: lui a1, 66
; RV32IF-NEXT: slli a0, a0, 2
; RV32IF-NEXT: addi a1, a1, 769
; RV32IF-NEXT: srl s0, a1, a0
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: andi s0, s0, 7
; RV32IF-NEXT: bnez s0, .LBB1_2
; RV32IF-NEXT: # %bb.1: # %if.end
; RV32IF-NEXT: call fesetround
; RV32IF-NEXT: addi s0, s0, -1
; RV32IF-NEXT: seqz a0, s0
; RV32IF-NEXT: .LBB1_2: # %return
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: .cfi_restore ra
; RV32IF-NEXT: .cfi_restore s0
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: .cfi_def_cfa_offset 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_get_rounding_sideeffect:
; RV64IF: # %bb.0: # %entry
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: .cfi_def_cfa_offset 16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IF-NEXT: .cfi_offset ra, -8
; RV64IF-NEXT: .cfi_offset s0, -16
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: call fesetround
; RV64IF-NEXT: frrm a0
; RV64IF-NEXT: lui a1, 66
; RV64IF-NEXT: slli a0, a0, 2
; RV64IF-NEXT: addiw a1, a1, 769
; RV64IF-NEXT: srl s0, a1, a0
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: andi s0, s0, 7
; RV64IF-NEXT: bnez s0, .LBB1_2
; RV64IF-NEXT: # %bb.1: # %if.end
; RV64IF-NEXT: call fesetround
; RV64IF-NEXT: addi s0, s0, -1
; RV64IF-NEXT: seqz a0, s0
; RV64IF-NEXT: .LBB1_2: # %return
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: .cfi_restore ra
; RV64IF-NEXT: .cfi_restore s0
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: .cfi_def_cfa_offset 0
; RV64IF-NEXT: ret
entry:
%call = tail call i32 @fesetround(i32 noundef 1) #0
%0 = tail call i32 @llvm.get.rounding() #0
%cmp.not = icmp eq i32 %0, 0
br i1 %cmp.not, label %if.end, label %return

if.end:
%call1 = tail call i32 @fesetround(i32 noundef 0) #0
%1 = tail call i32 @llvm.get.rounding() #0
%cmp2.not = icmp eq i32 %1, 1
br label %return

return:
%retval.0 = phi i1 [ false, %entry ], [ %cmp2.not, %if.end ]
ret i1 %retval.0
}

define void @func_02(i32 %rm) {
; RV32IF-LABEL: func_02:
; RV32IF: # %bb.0:
Expand Down Expand Up @@ -121,5 +200,9 @@ define void @func_07() {
ret void
}

attributes #0 = { strictfp }

declare void @llvm.set.rounding(i32)
declare i32 @llvm.get.rounding()
declare i32 @fesetround(i32 noundef)