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[LLVM][SVE] Relax optimizeIncrementingWhile constant operand requirements. #140037

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Merged
merged 2 commits into from
May 16, 2025
+10 −7
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[LLVM][SVE] Relax optimizeIncrementingWhile constant operand requirements. #140037

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f97648e
update test to show missing optimisation
paulwalker-arm May 14, 2025
710aef8
[LLVM][SVE] Relax optimizeIncrementingWhile constant operand requirem…
paulwalker-arm May 14, 2025
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9 changes: 6 additions & 3 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5744,12 +5744,10 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG,
unsigned Op0 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 1 : 0;
unsigned Op1 = N->getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 2 : 1;

if (!isa<ConstantSDNode>(N->getOperand(Op0)) ||
!isa<ConstantSDNode>(N->getOperand(Op1)))
if (!isa<ConstantSDNode>(N->getOperand(Op1)))
return SDValue();

SDLoc dl(N);
APInt X = N->getConstantOperandAPInt(Op0);
APInt Y = N->getConstantOperandAPInt(Op1);

// When the second operand is the maximum value, comparisons that include
Expand All @@ -5758,6 +5756,11 @@ static SDValue optimizeIncrementingWhile(SDNode *N, SelectionDAG &DAG,
if (IsSigned ? Y.isMaxSignedValue() : Y.isMaxValue())
return DAG.getConstant(1, dl, N->getValueType(0));

if (!isa<ConstantSDNode>(N->getOperand(Op0)))
return SDValue();

APInt X = N->getConstantOperandAPInt(Op0);

bool Overflow;
APInt NumActiveElems =
IsSigned ? Y.ssub_ov(X, Overflow) : Y.usub_ov(X, Overflow);
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
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Expand Up @@ -128,12 +128,12 @@ define <vscale x 16 x i1> @whilele_b_ii_dont_fold_to_ptrue_overflow() {
ret <vscale x 16 x i1> %out
}

define <vscale x 16 x i1> @whilele_b_ii_known_always_true() {
define <vscale x 16 x i1> @whilele_b_ii_known_always_true(i32 %a) {
; CHECK-LABEL: whilele_b_ii_known_always_true:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ret
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 2147483646, i32 2147483647)
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %a, i32 2147483647)
ret <vscale x 16 x i1> %out
}

Expand Down Expand Up @@ -387,12 +387,12 @@ define <vscale x 16 x i1> @whilels_b_ii_dont_fold_to_ptrue_overflow() {
ret <vscale x 16 x i1> %out
}

define <vscale x 16 x i1> @whilels_b_ii_known_always_true() {
define <vscale x 16 x i1> @whilels_b_ii_known_always_true(i32 %a) {
; CHECK-LABEL: whilels_b_ii_known_always_true:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: ret
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 4294967294, i32 4294967295)
%out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %a, i32 4294967295)
ret <vscale x 16 x i1> %out
}

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