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[RISCV] Add Andes A25/AX25 processor definition #140681

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Merged
merged 4 commits into from
May 22, 2025
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Merged

[RISCV] Add Andes A25/AX25 processor definition #140681

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80f55ea
[RISCV] Add Andes A25/AX25 processor definition
tclin914 May 20, 2025
989912e
Check print-enabled-extensions instead of checking -target-feature
tclin914 May 21, 2025
1013fbe
Replace Zba, Zbb and Zbs with B.
tclin914 May 21, 2025
f5e2cc4
Add extension xandesperf for A25/AX25
tclin914 May 21, 2025
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30 changes: 30 additions & 0 deletions clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c
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// RUN: %clang --target=riscv32 -mcpu=andes-a25 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target

// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:
// CHECK-NEXT: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
29 changes: 29 additions & 0 deletions clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c
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// RUN: %clang --target=riscv64 -mcpu=andes-ax25 --print-enabled-extensions | FileCheck %s
// REQUIRES: riscv-registered-target

// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:
// CHECK-NEXT: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication)
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
// CHECK-EMPTY:
// CHECK-NEXT: Experimental extensions
// CHECK-EMPTY:
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0
16 changes: 16 additions & 0 deletions clang/test/Driver/riscv-cpus.c
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Expand Up @@ -699,6 +699,22 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a25 | FileCheck -check-prefix=MCPU-ANDES-A25 %s
// MCPU-ANDES-A25: "-target-cpu" "andes-a25"
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a25.c`
// MCPU-ANDES-A25-SAME: "-target-abi" "ilp32d"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a25 | FileCheck -check-prefix=MTUNE-ANDES-A25 %s
// MTUNE-ANDES-A25: "-tune-cpu" "andes-a25"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax25 | FileCheck -check-prefix=MCPU-ANDES-AX25 %s
// MCPU-ANDES-AX25: "-target-cpu" "andes-ax25"
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax25.c`
// MCPU-ANDES-AX25-SAME: "-target-abi" "lp64d"

// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax25 | FileCheck -check-prefix=MTUNE-ANDES-AX25 %s
// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"

// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
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12 changes: 8 additions & 4 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Expand Up @@ -5,7 +5,8 @@
// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
// RISCV32: error: unknown target CPU 'not-a-cpu'
// RISCV32-NEXT: note: valid target CPU values are:
// RISCV32-SAME: {{^}} andes-a45
// RISCV32-SAME: {{^}} andes-a25
// RISCV32-SAME: {{^}}, andes-a45
// RISCV32-SAME: {{^}}, andes-n45
// RISCV32-SAME: {{^}}, generic-rv32
// RISCV32-SAME: {{^}}, rocket-rv32
Expand All @@ -26,7 +27,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
// RISCV64: error: unknown target CPU 'not-a-cpu'
// RISCV64-NEXT: note: valid target CPU values are:
// RISCV64-SAME: {{^}} andes-ax45
// RISCV64-SAME: {{^}} andes-ax25
// RISCV64-SAME: {{^}}, andes-ax45
// RISCV64-SAME: {{^}}, andes-nx45
// RISCV64-SAME: {{^}}, generic-rv64
// RISCV64-SAME: {{^}}, mips-p8700
Expand Down Expand Up @@ -57,7 +59,8 @@
// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV32-NEXT: note: valid target CPU values are:
// TUNE-RISCV32-SAME: {{^}} andes-a45
// TUNE-RISCV32-SAME: {{^}} andes-a25
// TUNE-RISCV32-SAME: {{^}}, andes-a45
// TUNE-RISCV32-SAME: {{^}}, andes-n45
// TUNE-RISCV32-SAME: {{^}}, generic-rv32
// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
Expand All @@ -82,7 +85,8 @@
// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
// TUNE-RISCV64-NEXT: note: valid target CPU values are:
// TUNE-RISCV64-SAME: {{^}} andes-ax45
// TUNE-RISCV64-SAME: {{^}} andes-ax25
// TUNE-RISCV64-SAME: {{^}}, andes-ax45
// TUNE-RISCV64-SAME: {{^}}, andes-nx45
// TUNE-RISCV64-SAME: {{^}}, generic-rv64
// TUNE-RISCV64-SAME: {{^}}, mips-p8700
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -199,6 +199,7 @@ Changes to the RISC-V Backend
extension.
* Adds experimental assembler support for the SiFive Xsfmm* Attached Matrix
Extensions.
* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.

Changes to the WebAssembly Backend
----------------------------------
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30 changes: 30 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -648,6 +648,36 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
FeatureStdExtZcb,
FeatureStdExtZcmp]>;

def ANDES_A25 : RISCVProcessorModel<"andes-a25",
NoSchedModel,
[Feature32Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;

def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
NoSchedModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtB,
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;

def ANDES_N45 : RISCVProcessorModel<"andes-n45",
NoSchedModel,
[Feature32Bit,
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