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AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum #140900

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Merged
merged 1 commit into from
May 21, 2025
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AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum #140900

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31 changes: 29 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3221,6 +3221,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
case TargetOpcode::G_FMAXNUM_IEEE:
case TargetOpcode::G_FMINIMUM:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
case TargetOpcode::G_FDIV:
case TargetOpcode::G_FREM:
case TargetOpcode::G_FCEIL:
Expand Down Expand Up @@ -4591,6 +4593,8 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
return lowerFCopySign(MI);
case G_FMINNUM:
case G_FMAXNUM:
case G_FMINIMUMNUM:
case G_FMAXIMUMNUM:
return lowerFMinNumMaxNum(MI);
case G_MERGE_VALUES:
return lowerMergeValues(MI);
Expand Down Expand Up @@ -5379,6 +5383,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
case G_FMAXNUM_IEEE:
case G_FMINIMUM:
case G_FMAXIMUM:
case G_FMINIMUMNUM:
case G_FMAXIMUMNUM:
case G_FSHL:
case G_FSHR:
case G_ROTL:
Expand Down Expand Up @@ -6090,6 +6096,8 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
case TargetOpcode::G_FMAXNUM_IEEE:
case TargetOpcode::G_FMINIMUM:
case TargetOpcode::G_FMAXIMUM:
case TargetOpcode::G_FMINIMUMNUM:
case TargetOpcode::G_FMAXIMUMNUM:
case TargetOpcode::G_STRICT_FADD:
case TargetOpcode::G_STRICT_FSUB:
case TargetOpcode::G_STRICT_FMUL:
Expand Down Expand Up @@ -8139,8 +8147,27 @@ LegalizerHelper::lowerFCopySign(MachineInstr &MI) {

LegalizerHelper::LegalizeResult
LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
// FIXME: fminnum/fmaxnum and fminimumnum/fmaximumnum should not have
// identical handling. fminimumnum/fmaximumnum also need a path that do not
// depend on fminnum/fmaxnum.

unsigned NewOp;
switch (MI.getOpcode()) {
case TargetOpcode::G_FMINNUM:
NewOp = TargetOpcode::G_FMINNUM_IEEE;
break;
case TargetOpcode::G_FMINIMUMNUM:
NewOp = TargetOpcode::G_FMINNUM;
break;
case TargetOpcode::G_FMAXNUM:
NewOp = TargetOpcode::G_FMAXNUM_IEEE;
break;
case TargetOpcode::G_FMAXIMUMNUM:
NewOp = TargetOpcode::G_FMAXNUM;
break;
default:
llvm_unreachable("unexpected min/max opcode");
}

auto [Dst, Src0, Src1] = MI.getFirst3Regs();
LLT Ty = MRI.getType(Dst);
Expand Down
6 changes: 6 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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Expand Up @@ -960,6 +960,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &MinNumMaxNum = getActionDefinitionsBuilder({
G_FMINNUM, G_FMAXNUM, G_FMINNUM_IEEE, G_FMAXNUM_IEEE});

// TODO: These should be custom lowered and are directly legal with IEEE=0
auto &MinimumNumMaximumNum =
getActionDefinitionsBuilder({G_FMINIMUMNUM, G_FMAXIMUMNUM});

if (ST.hasVOP3PInsts()) {
MinNumMaxNum.customFor(FPTypesPK16)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
Expand All @@ -976,6 +980,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.scalarize(0);
}

MinimumNumMaximumNum.lower();

if (ST.hasVOP3PInsts())
FPOpActions.clampMaxNumElementsStrict(0, S16, 2);

Expand Down
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