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[RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 #141007

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Merged
merged 1 commit into from
May 22, 2025
Merged

[RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 #141007

merged 1 commit into from
May 22, 2025

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tclin914
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Andes N45/NX45/A45/AX45 also support XAndesPerf.

@tclin914
[RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45
655b5cb 
Andes N45/NX45/A45/AX45 also support XAndesPerf.
@tclin914 tclin914 requested review from kito-cheng and mshockwave May 22, 2025 05:07
@llvmbot llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' labels May 22, 2025
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llvmbot commented May 22, 2025 •
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@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-clang

Author: Jim Lin (tclin914)

Changes

Andes N45/NX45/A45/AX45 also support XAndesPerf.

Full diff: https://github.com/llvm/llvm-project/pull/141007.diff

5 Files Affected:

  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c (+2-1)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c (+2-1)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c (+2-1)
  • (modified) clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c (+2-1)
  • (modified) llvm/lib/Target/RISCV/RISCVProcessors.td (+8-4)
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
index b1cecfbb0ff32..a0a1c35911409 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c
@@ -22,7 +22,8 @@
 // CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
 // CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
 // CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
 // CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
index a47e7f0cbd05f..6460d701411bc 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c
@@ -21,7 +21,8 @@
 // CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
 // CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
 // CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
 // CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
index fa4ceb8b13c0e..4d9c514b756e6 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c
@@ -22,7 +22,8 @@
 // CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
 // CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
 // CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
 // CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c
index fdb3be3d38073..5eaada3f9e164 100644
--- a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c
+++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c
@@ -21,7 +21,8 @@
 // CHECK-NEXT:     zba                  1.0       'Zba' (Address Generation Instructions)
 // CHECK-NEXT:     zbb                  1.0       'Zbb' (Basic Bit-Manipulation)
 // CHECK-NEXT:     zbs                  1.0       'Zbs' (Single-Bit Instructions)
+// CHECK-NEXT:     xandesperf           5.0       'XAndesPerf' (Andes Performance Extension)
 // CHECK-EMPTY:
 // CHECK-NEXT: Experimental extensions
 // CHECK-EMPTY:
-// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0
+// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 419609807bda9..dc0ae384d6b08 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -689,7 +689,8 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB]>;
+                                     FeatureStdExtB,
+                                     FeatureVendorXAndesPerf]>;
 
 def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
                                      NoSchedModel,
@@ -702,7 +703,8 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB]>;
+                                      FeatureStdExtB,
+                                      FeatureVendorXAndesPerf]>;
 
 def ANDES_A45 : RISCVProcessorModel<"andes-a45",
                                     NoSchedModel,
@@ -715,7 +717,8 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45",
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC,
-                                     FeatureStdExtB]>;
+                                     FeatureStdExtB,
+                                     FeatureVendorXAndesPerf]>;
 
 def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
                                      NoSchedModel,
@@ -728,4 +731,5 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45",
                                       FeatureStdExtF,
                                       FeatureStdExtD,
                                       FeatureStdExtC,
-                                      FeatureStdExtB]>;
+                                      FeatureStdExtB,
+                                      FeatureVendorXAndesPerf]>;

@tclin914 tclin914 requested a review from topperc May 22, 2025 05:24
kito-cheng
kito-cheng approved these changes May 22, 2025
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LGTM

@tclin914 tclin914 merged commit 04211ba into llvm:main May 22, 2025
15 checks passed
@tclin914 tclin914 deleted the andes-cpu-45-xandesperf branch May 22, 2025 06:42
sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Jun 3, 2025
@tclin914 @sivan-shani
[RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (llvm#…
3e43981 
…141007)

Andes N45/NX45/A45/AX45 also support XAndesPerf.
ajaden-codes pushed a commit to Jaddyen/llvm-project that referenced this pull request Jun 6, 2025
@tclin914 @Jaddyen
[RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (llvm#…
7ab9378 
…141007)

Andes N45/NX45/A45/AX45 also support XAndesPerf.
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@kito-cheng kito-cheng kito-cheng approved these changes

@mshockwave mshockwave Awaiting requested review from mshockwave

@topperc topperc Awaiting requested review from topperc

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