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Merged
merged 1 commit into from
May 23, 2025

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@heiher heiher commented May 22, 2025

Took xry's idea 1 to improve the csrxchg instrinsic test case.

Footnotes

  1. https://github.com/llvm/llvm-project/pull/141037#issuecomment-2900955906

Took xry's idea [^1] to improve the csrxchg instrinsic test case.

[^1]: llvm#141037 (comment)
@llvmbot
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llvmbot commented May 22, 2025

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

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Took xry's idea 1 to improve the csrxchg instrinsic test case.


Full diff: https://github.com/llvm/llvm-project/pull/141060.diff

1 Files Affected:

  • (modified) llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll (+4-5)
diff --git a/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll b/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
index 2f38b3a8c7ad1..cdeb7a008b848 100644
--- a/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
+++ b/llvm/test/CodeGen/LoongArch/csrxchg-intrinsic.ll
@@ -13,12 +13,11 @@ entry:
 }
 
 ;; Check that the rj operand of csrxchg is not R1.
-define i32 @csrxchg_w_rj_not_r1() {
+define i32 @csrxchg_w_rj_not_r1(i32 %0) {
 ; CHECK-NOT:    csrxchg ${{[a-z]*}}, $r1, 0
 ; CHECK-NOT:    csrxchg ${{[a-z]*}}, $ra, 0
 entry:
-  %0 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
-  %1 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %0, i32 4, i32 0)
-  %2 = tail call i32 asm "", "=r,r,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 %1)
-  ret i32 %2
+  %2 = tail call i32 asm "", "={$r1},{$r1}"(i32 0)
+  %3 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %0, i32 %2, i32 0)
+  ret i32 %3
 }

Footnotes

  1. https://github.com/llvm/llvm-project/pull/141037#issuecomment-2900955906

@heiher heiher requested a review from tangaac May 22, 2025 14:08
@heiher heiher merged commit 0635ef8 into llvm:main May 23, 2025
13 checks passed
@heiher heiher deleted the csrxchg-test branch May 23, 2025 01:30
sivan-shani pushed a commit to sivan-shani/llvm-project that referenced this pull request Jun 3, 2025
Took xry's idea [^1] to improve the csrxchg instrinsic test case.

[^1]:
llvm#141037 (comment)
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3 participants