[RISCV] Select unsigned bitfield extracts for XAndesPerf

[tclin914]

The XAndesPerf extension includes unsigned bitfield extraction instruction
NDS.BFOZ, which can extract the bits from LSB to MSB, places them starting
at bit 0, and zero-extends the result.

The testcase includes the three patterns that can be selected as unsigned bitfield extracts:
and, and+lshr and lshr+and

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Jim Lin (tclin914)

Changes

Select NDS_BFOS for and operation with trailing ones mask. The msb
operand is calculated as the number of trailing ones minus one.

---

Full diff: https://github.com/llvm/llvm-project/pull/141398.diff

4 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+5)
• (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td (+3)
• (modified) llvm/test/CodeGen/RISCV/rv32xandesperf.ll (+20)
• (modified) llvm/test/CodeGen/RISCV/rv64xandesperf.ll (+18)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 9058934557b54..8dc04d6dcd852 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -564,6 +564,11 @@ def XLenSubTrailingOnes : SDNodeXForm<imm, [{
 def GIXLenSubTrailingOnes : GICustomOperandRenderer<"renderXLenSubTrailingOnes">,
   GISDNodeXFormEquiv<XLenSubTrailingOnes>;
 
+def TrailingOnesSubOne : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()) - 1,
+                                   SDLoc(N), N->getValueType(0));
+}]>;
+
 // Checks if this mask is a non-empty sequence of ones starting at the
 // most/least significant bit with the remainder zero and exceeds simm32/simm12.
 def LeadingOnesMask : ImmLeaf<XLenVT, [{
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
index ec883cd1d3157..686cc0bc47be8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td
@@ -466,6 +466,9 @@ def NDS_VD4DOTSU_VV : NDSRVInstVD4DOT<0b000101, "nds.vd4dotsu">;
 
 let Predicates = [HasVendorXAndesPerf] in {
 
+def : Pat<(XLenVT (and GPR:$rs, TrailingOnesMask:$mask)),
+          (NDS_BFOZ $rs, (TrailingOnesSubOne imm:$mask), 0)>;
+
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i16), (NDS_BFOS GPR:$rs1, 15, 0)>;
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i8), (NDS_BFOS GPR:$rs1, 7, 0)>;
 def : Pat<(sext_inreg (XLenVT GPR:$rs1), i1), (NDS_BFOS GPR:$rs1, 0, 0)>;
diff --git a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
index efe5b4a306fee..d15725a3b3b3b 100644
--- a/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
+++ b/llvm/test/CodeGen/RISCV/rv32xandesperf.ll
@@ -2,6 +2,26 @@
 ; RUN: llc -O0 -mtriple=riscv32 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+define i32 @and32_0xfff(i32 %x) {
+; CHECK-LABEL: and32_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
+; CHECK-NEXT:    ret
+  %a = and i32 %x, 4095
+  ret i32 %a
+}
+
+define i64 @and64_0xfff(i64 %x) {
+; CHECK-LABEL: and64_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    # kill: def $x11 killed $x10
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
+; CHECK-NEXT:    li a1, 0
+; CHECK-NEXT:    ret
+  %a = and i64 %x, 4095
+  ret i64 %a
+}
+
 define i32 @sexti1_i32(i32 %a) {
 ; CHECK-LABEL: sexti1_i32:
 ; CHECK:       # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64xandesperf.ll b/llvm/test/CodeGen/RISCV/rv64xandesperf.ll
index 9cc95ce886133..1b6d2a8287de7 100644
--- a/llvm/test/CodeGen/RISCV/rv64xandesperf.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xandesperf.ll
@@ -2,6 +2,24 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
+define i32 @and32_0xfff(i32 %x) {
+; CHECK-LABEL: and32_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
+; CHECK-NEXT:    ret
+  %a = and i32 %x, 4095
+  ret i32 %a
+}
+
+define i64 @and64_0xfff(i64 %x) {
+; CHECK-LABEL: and64_0xfff:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    nds.bfoz a0, a0, 11, 0
+; CHECK-NEXT:    ret
+  %a = and i64 %x, 4095
+  ret i64 %a
+}
+
 define signext i32 @sexti1_i32(i32 signext %a) {
 ; CHECK-LABEL: sexti1_i32:
 ; CHECK:       # %bb.0:

[topperc]

LGTM