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[AArch64] Handle XAR with v1i64 operand types #141754

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May 29, 2025
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[AArch64] Handle XAR with v1i64 operand types #141754

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[AArch64] Handle XAR with v1i64 operand types
davemgreen May 28, 2025
38aa26b
Update llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
davemgreen May 29, 2025
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27 changes: 25 additions & 2 deletions llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4637,15 +4637,38 @@ bool AArch64DAGToDAGISel::trySelectXAR(SDNode *N) {

if (!IsXOROperand) {
SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i64);
SDNode *MOV = CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, VT, Zero);
SDNode *MOV =
CurDAG->getMachineNode(AArch64::MOVIv2d_ns, DL, MVT::v2i64, Zero);
SDValue MOVIV = SDValue(MOV, 0);
R1 = N1->getOperand(0);
R2 = MOVIV;
}

// If the input is a v1i64, widen to a v2i64 to use XAR.
assert((VT == MVT::v1i64 || VT == MVT::v2i64) && "Unexpected XAR type!");
if (VT == MVT::v1i64) {
EVT SVT = MVT::v2i64;
SDValue Undef =
SDValue(CurDAG->getMachineNode(AArch64::IMPLICIT_DEF, DL, SVT), 0);
SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
R1 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT, Undef,
R1, DSub),
0);
if (R2.getValueType() == MVT::v1i64)
R2 = SDValue(CurDAG->getMachineNode(AArch64::INSERT_SUBREG, DL, SVT,
Undef, R2, DSub),
0);
}

SDValue Ops[] = {R1, R2, Imm};
CurDAG->SelectNodeTo(N, AArch64::XAR, N0.getValueType(), Ops);
SDNode *XAR = CurDAG->getMachineNode(AArch64::XAR, DL, MVT::v2i64, Ops);

if (VT == MVT::v1i64) {
SDValue DSub = CurDAG->getTargetConstant(AArch64::dsub, DL, MVT::i32);
XAR = CurDAG->getMachineNode(AArch64::EXTRACT_SUBREG, DL, VT,
SDValue(XAR, 0), DSub);
}
ReplaceNode(N, XAR);
return true;
}

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39 changes: 39 additions & 0 deletions llvm/test/CodeGen/AArch64/xar.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,26 @@ define <2 x i64> @xar(<2 x i64> %x, <2 x i64> %y) {
ret <2 x i64> %b
}

define <1 x i64> @xar_v1i64(<1 x i64> %a, <1 x i64> %b) {
; SHA3-LABEL: xar_v1i64:
; SHA3: // %bb.0:
; SHA3-NEXT: // kill: def $d0 killed $d0 def $q0
; SHA3-NEXT: // kill: def $d1 killed $d1 def $q1
; SHA3-NEXT: xar v0.2d, v0.2d, v1.2d, #63
; SHA3-NEXT: // kill: def $d0 killed $d0 killed $q0
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: xar_v1i64:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: eor v1.8b, v0.8b, v1.8b
; NOSHA3-NEXT: shl d0, d1, #1
; NOSHA3-NEXT: usra d0, d1, #63
; NOSHA3-NEXT: ret
%v.val = xor <1 x i64> %a, %b
%fshl = tail call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %v.val, <1 x i64> %v.val, <1 x i64> splat (i64 1))
ret <1 x i64> %fshl
}

define <2 x i64> @xar_instead_of_or1(<2 x i64> %r) {
; SHA3-LABEL: xar_instead_of_or1:
; SHA3: // %bb.0: // %entry
Expand All @@ -37,6 +57,25 @@ entry:
ret <2 x i64> %or
}

define <1 x i64> @xar_instead_of_or_v1i64(<1 x i64> %v.val) {
; SHA3-LABEL: xar_instead_of_or_v1i64:
; SHA3: // %bb.0:
; SHA3-NEXT: movi v1.2d, #0000000000000000
; SHA3-NEXT: // kill: def $d0 killed $d0 def $q0
; SHA3-NEXT: xar v0.2d, v0.2d, v1.2d, #63
; SHA3-NEXT: // kill: def $d0 killed $d0 killed $q0
; SHA3-NEXT: ret
;
; NOSHA3-LABEL: xar_instead_of_or_v1i64:
; NOSHA3: // %bb.0:
; NOSHA3-NEXT: shl d1, d0, #1
; NOSHA3-NEXT: usra d1, d0, #63
; NOSHA3-NEXT: fmov d0, d1
; NOSHA3-NEXT: ret
%fshl = tail call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %v.val, <1 x i64> %v.val, <1 x i64> splat (i64 1))
ret <1 x i64> %fshl
}

define <4 x i32> @xar_instead_of_or2(<4 x i32> %r) {
; SHA3-LABEL: xar_instead_of_or2:
; SHA3: // %bb.0: // %entry
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