[RISCV] Add X0_Pair to RISCVDeadRegisterDefinitions. #141831
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesFull diff: https://github.com/llvm/llvm-project/pull/141831.diff 3 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
index 47510ec6b0ea8..2f4bdb7b64f4e 100644
--- a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
+++ b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
@@ -99,6 +99,8 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
X0Reg = RISCV::X0_W;
} else if (RC && RC->contains(RISCV::X0_H)) {
X0Reg = RISCV::X0_H;
+ } else if (RC && RC->contains(RISCV::X0_Pair)) {
+ X0Reg = RISCV::X0_Pair;
} else {
LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
continue;
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index 0210e0252deca..81ef194da8b47 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -141,10 +141,10 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; RV32IZFINXZDINXZILSD: # %bb.0:
; RV32IZFINXZDINXZILSD-NEXT: lui a4, %hi(G)
; RV32IZFINXZDINXZILSD-NEXT: fadd.d a0, a0, a2
-; RV32IZFINXZDINXZILSD-NEXT: ld a2, %lo(G)(a4)
+; RV32IZFINXZDINXZILSD-NEXT: ld zero, %lo(G)(a4)
; RV32IZFINXZDINXZILSD-NEXT: addi a2, a4, %lo(G)
; RV32IZFINXZDINXZILSD-NEXT: sd a0, %lo(G)(a4)
-; RV32IZFINXZDINXZILSD-NEXT: ld a4, 72(a2)
+; RV32IZFINXZDINXZILSD-NEXT: ld zero, 72(a2)
; RV32IZFINXZDINXZILSD-NEXT: sd a0, 72(a2)
; RV32IZFINXZDINXZILSD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
diff --git a/llvm/test/CodeGen/RISCV/zilsd.ll b/llvm/test/CodeGen/RISCV/zilsd.ll
index 3eaaffba250dd..bc2f7d486f16b 100644
--- a/llvm/test/CodeGen/RISCV/zilsd.ll
+++ b/llvm/test/CodeGen/RISCV/zilsd.ll
@@ -8,7 +8,7 @@ define i64 @load(ptr %a) nounwind {
; CHECK-LABEL: load:
; CHECK: # %bb.0:
; CHECK-NEXT: ld a2, 80(a0)
-; CHECK-NEXT: ld a0, 0(a0)
+; CHECK-NEXT: ld zero, 0(a0)
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: mv a1, a3
; CHECK-NEXT: ret
|
lenary
approved these changes
May 28, 2025
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/16711 Here is the relevant piece of the build log for the reference |
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