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[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args #141959

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Merged
merged 3 commits into from
Jun 5, 2025
Merged

[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args #141959

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4d055df
[GlobalISel] support lowering of G_SHUFFLEVECTOR with pointer args
stanleygambarin May 29, 2025
a7c31d7
fix recommendations
stanleygambarin May 29, 2025
fc4a1d3
update test
stanleygambarin May 30, 2025
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6 changes: 3 additions & 3 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8446,10 +8446,10 @@ LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
}
}

if (DstTy.isScalar())
MIRBuilder.buildCopy(DstReg, BuildVec[0]);
else
if (DstTy.isVector())
MIRBuilder.buildBuildVector(DstReg, BuildVec);
else
MIRBuilder.buildCopy(DstReg, BuildVec[0]);
MI.eraseFromParent();
return Legalized;
}
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36 changes: 36 additions & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector-pointer-crash.mir
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@@ -0,0 +1,36 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s

---
name: test
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[C]](p0) :: (load (s32), align 16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 4
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[C1]](p0) :: (load (s32) from unknown-address + 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 8
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[C2]](p0) :: (load (s32) from unknown-address + 8, align 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 12
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[C3]](p0) :: (load (s32) from unknown-address + 12)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[BITCAST]](<2 x p0>)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[UV]](p0)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[UV3]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
%0:_(p0) = G_CONSTANT i64 0
%1:_(<2 x p0>) = G_BUILD_VECTOR %0:_(p0), %0:_(p0)
%2:_(<2 x p0>) = G_LOAD %0:_(p0) :: (load (<2 x p0>))
%3:_(p0) = G_SHUFFLE_VECTOR %2:_(<2 x p0>), %1:_, shufflemask(0)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3:_(p0)
$vgpr0 = COPY %4:_(s32)
$vgpr1 = COPY %5:_(s32)
SI_RETURN implicit $vgpr0, implicit $vgpr1
...