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[RISCV] Fix a bug in partial.reduce lowering for zvqdotq .vx forms #142185

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Merged
merged 1 commit into from
May 30, 2025
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[RISCV] Fix a bug in partial.reduce lowering for zvqdotq .vx forms #142185

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11 changes: 8 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8412,13 +8412,18 @@ SDValue RISCVTargetLowering::lowerPARTIAL_REDUCE_MLA(SDValue Op,
assert(ArgVT == B.getSimpleValueType() &&
ArgVT.getVectorElementType() == MVT::i8);

// The zvqdotq pseudos are defined with sources and destination both
// being i32. This cast is needed for correctness to avoid incorrect
// .vx matching of i8 splats.
A = DAG.getBitcast(VT, A);
B = DAG.getBitcast(VT, B);

MVT ContainerVT = VT;
if (VT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(VT);
Accum = convertToScalableVector(ContainerVT, Accum, DAG, Subtarget);
MVT ArgContainerVT = getContainerForFixedLengthVector(ArgVT);
A = convertToScalableVector(ArgContainerVT, A, DAG, Subtarget);
B = convertToScalableVector(ArgContainerVT, B, DAG, Subtarget);
A = convertToScalableVector(ContainerVT, A, DAG, Subtarget);
B = convertToScalableVector(ContainerVT, B, DAG, Subtarget);
}

bool IsSigned = Op.getOpcode() == ISD::PARTIAL_REDUCE_SMLA;
Expand Down
28 changes: 16 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -598,7 +598,6 @@ entry:
ret <1 x i32> %res
}

; FIXME: This case is wrong. We should be splatting 128 to each i8 lane!
define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-LABEL: vqdotu_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
Expand All @@ -618,10 +617,13 @@ define <1 x i32> @vqdotu_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
;
; DOT-LABEL: vqdotu_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
; DOT-NEXT: li a0, 128
; DOT-NEXT: vqdotu.vx v9, v8, a0
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vqdotu.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
Expand All @@ -631,7 +633,6 @@ entry:
ret <1 x i32> %res
}

; FIXME: This case is wrong. We should be splatting 128 to each i8 lane!
define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
; NODOT-LABEL: vqdot_vx_partial_reduce:
; NODOT: # %bb.0: # %entry
Expand All @@ -652,10 +653,13 @@ define <1 x i32> @vqdot_vx_partial_reduce(<4 x i8> %a, <4 x i8> %b) {
;
; DOT-LABEL: vqdot_vx_partial_reduce:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; DOT-NEXT: vmv.s.x v9, zero
; DOT-NEXT: li a0, 128
; DOT-NEXT: vqdot.vx v9, v8, a0
; DOT-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; DOT-NEXT: vmv.v.x v10, a0
; DOT-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; DOT-NEXT: vqdot.vv v9, v8, v10
; DOT-NEXT: vmv1r.v v8, v9
; DOT-NEXT: ret
entry:
Expand Down Expand Up @@ -1372,7 +1376,6 @@ entry:
}


; FIXME: This case is wrong. We should be splatting 128 to each i8 lane!
define <4 x i32> @partial_of_sext(<16 x i8> %a) {
; NODOT-LABEL: partial_of_sext:
; NODOT: # %bb.0: # %entry
Expand All @@ -1393,10 +1396,11 @@ define <4 x i32> @partial_of_sext(<16 x i8> %a) {
;
; DOT-LABEL: partial_of_sext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
; DOT-NEXT: li a0, 1
; DOT-NEXT: vqdot.vx v9, v8, a0
; DOT-NEXT: vqdot.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
Expand All @@ -1405,7 +1409,6 @@ entry:
ret <4 x i32> %res
}

; FIXME: This case is wrong. We should be splatting 128 to each i8 lane!
define <4 x i32> @partial_of_zext(<16 x i8> %a) {
; NODOT-LABEL: partial_of_zext:
; NODOT: # %bb.0: # %entry
Expand All @@ -1426,10 +1429,11 @@ define <4 x i32> @partial_of_zext(<16 x i8> %a) {
;
; DOT-LABEL: partial_of_zext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
; DOT-NEXT: li a0, 1
; DOT-NEXT: vqdotu.vx v9, v8, a0
; DOT-NEXT: vqdotu.vv v9, v8, v10
; DOT-NEXT: vmv.v.v v8, v9
; DOT-NEXT: ret
entry:
Expand Down
53 changes: 53 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
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Expand Up @@ -957,3 +957,56 @@ entry:
%res = call <vscale x 1 x i32> @llvm.experimental.vector.partial.reduce.add(<vscale x 1 x i32> zeroinitializer, <vscale x 4 x i32> %mul)
ret <vscale x 1 x i32> %res
}


define <vscale x 4 x i32> @partial_of_sext(<vscale x 16 x i8> %a) {
; NODOT-LABEL: partial_of_sext:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; NODOT-NEXT: vsext.vf4 v16, v8
; NODOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; NODOT-NEXT: vadd.vv v8, v22, v16
; NODOT-NEXT: vadd.vv v10, v18, v20
; NODOT-NEXT: vadd.vv v8, v10, v8
; NODOT-NEXT: ret
;
; DOT-LABEL: partial_of_sext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: vqdot.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
%a.ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i32>
%res = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i32> %a.ext)
ret <vscale x 4 x i32> %res
}

define <vscale x 4 x i32> @partial_of_zext(<vscale x 16 x i8> %a) {
; NODOT-LABEL: partial_of_zext:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; NODOT-NEXT: vzext.vf4 v16, v8
; NODOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; NODOT-NEXT: vadd.vv v8, v22, v16
; NODOT-NEXT: vadd.vv v10, v18, v20
; NODOT-NEXT: vadd.vv v8, v10, v8
; NODOT-NEXT: ret
;
; DOT-LABEL: partial_of_zext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; DOT-NEXT: vmv.v.i v12, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: vqdotu.vv v10, v8, v12
; DOT-NEXT: vmv.v.v v8, v10
; DOT-NEXT: ret
entry:
%a.ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i32>
%res = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add(<vscale x 4 x i32> zeroinitializer, <vscale x 16 x i32> %a.ext)
ret <vscale x 4 x i32> %res
}
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