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[RISCV] Migrate zvqdotq reduce matching to use partial_reduce infrastructure #142212

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Merged
merged 7 commits into from
Jun 10, 2025
Merged

[RISCV] Migrate zvqdotq reduce matching to use partial_reduce infrastructure #142212

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[RISCV] Migrate zvqdotq reduce matching to use partial_reduce infrast…
preames May 30, 2025
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clang-format
preames May 30, 2025
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Merge branch 'main' into pr-zvqdotq-reduce-of-ext-via-partial-reduce
preames Jun 9, 2025
bde6cfd
Use parial_reduce_sumla
preames Jun 9, 2025
e877de0
Style and comment cleanup
preames Jun 9, 2025
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Delete dead code
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100 changes: 38 additions & 62 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18372,31 +18372,6 @@ static SDValue performBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
DAG.getBuildVector(VT, DL, RHSOps));
}

static SDValue lowerVQDOT(unsigned Opc, SDValue Op0, SDValue Op1,
const SDLoc &DL, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) {
assert(RISCVISD::VQDOT_VL == Opc || RISCVISD::VQDOTU_VL == Opc ||
RISCVISD::VQDOTSU_VL == Opc);
MVT VT = Op0.getSimpleValueType();
assert(VT == Op1.getSimpleValueType() &&
VT.getVectorElementType() == MVT::i32);

SDValue Passthru = DAG.getConstant(0, DL, VT);
MVT ContainerVT = VT;
if (VT.isFixedLengthVector()) {
ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
Passthru = convertToScalableVector(ContainerVT, Passthru, DAG, Subtarget);
Op0 = convertToScalableVector(ContainerVT, Op0, DAG, Subtarget);
Op1 = convertToScalableVector(ContainerVT, Op1, DAG, Subtarget);
}
auto [Mask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
SDValue LocalAccum = DAG.getNode(Opc, DL, ContainerVT,
{Op0, Op1, Passthru, Mask, VL});
if (VT.isFixedLengthVector())
return convertFromScalableVector(VT, LocalAccum, DAG, Subtarget);
return LocalAccum;
}

static MVT getQDOTXResultType(MVT OpVT) {
ElementCount OpEC = OpVT.getVectorElementCount();
assert(OpEC.isKnownMultipleOf(4) && OpVT.getVectorElementType() == MVT::i8);
Expand Down Expand Up @@ -18455,61 +18430,62 @@ static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
}
}

// reduce (zext a) <--> reduce (mul zext a. zext 1)
// reduce (sext a) <--> reduce (mul sext a. sext 1)
// zext a <--> partial_reduce_umla 0, a, 1
// sext a <--> partial_reduce_smla 0, a, 1
if (InVec.getOpcode() == ISD::ZERO_EXTEND ||
InVec.getOpcode() == ISD::SIGN_EXTEND) {
SDValue A = InVec.getOperand(0);
if (A.getValueType().getVectorElementType() != MVT::i8 ||
!TLI.isTypeLegal(A.getValueType()))
EVT OpVT = A.getValueType();
if (OpVT.getVectorElementType() != MVT::i8 || !TLI.isTypeLegal(OpVT))
return SDValue();

MVT ResVT = getQDOTXResultType(A.getSimpleValueType());
A = DAG.getBitcast(ResVT, A);
SDValue B = DAG.getConstant(0x01010101, DL, ResVT);

SDValue B = DAG.getConstant(0x1, DL, OpVT);
bool IsSigned = InVec.getOpcode() == ISD::SIGN_EXTEND;
unsigned Opc = IsSigned ? RISCVISD::VQDOT_VL : RISCVISD::VQDOTU_VL;
return lowerVQDOT(Opc, A, B, DL, DAG, Subtarget);
unsigned Opc =
IsSigned ? ISD::PARTIAL_REDUCE_SMLA : ISD::PARTIAL_REDUCE_UMLA;
return DAG.getNode(Opc, DL, ResVT, {DAG.getConstant(0, DL, ResVT), A, B});
}

// mul (sext, sext) -> vqdot
// mul (zext, zext) -> vqdotu
// mul (sext, zext) -> vqdotsu
// mul (zext, sext) -> vqdotsu (swapped)
// TODO: Improve .vx handling - we end up with a sub-vector insert
// which confuses the splat pattern matching. Also, match vqdotus.vx
// mul (sext a, sext b) -> partial_reduce_smla 0, a, b
// mul (zext a, zext b) -> partial_reduce_umla 0, a, b
// mul (sext a, zext b) -> partial_reduce_ssmla 0, a, b
// mul (zext a, sext b) -> partial_reduce_smla 0, b, a (swapped)
if (InVec.getOpcode() != ISD::MUL)
return SDValue();

SDValue A = InVec.getOperand(0);
SDValue B = InVec.getOperand(1);
unsigned Opc = 0;
if (A.getOpcode() == B.getOpcode()) {
if (A.getOpcode() == ISD::SIGN_EXTEND)
Opc = RISCVISD::VQDOT_VL;
else if (A.getOpcode() == ISD::ZERO_EXTEND)
Opc = RISCVISD::VQDOTU_VL;
else
return SDValue();
} else {
if (B.getOpcode() != ISD::ZERO_EXTEND)
std::swap(A, B);
if (A.getOpcode() != ISD::SIGN_EXTEND || B.getOpcode() != ISD::ZERO_EXTEND)
return SDValue();
Opc = RISCVISD::VQDOTSU_VL;
}
assert(Opc);

if (A.getOperand(0).getValueType().getVectorElementType() != MVT::i8 ||
A.getOperand(0).getValueType() != B.getOperand(0).getValueType() ||
if (!ISD::isExtOpcode(A.getOpcode()))
return SDValue();

EVT OpVT = A.getOperand(0).getValueType();
if (OpVT.getVectorElementType() != MVT::i8 ||
OpVT != B.getOperand(0).getValueType() ||
!TLI.isTypeLegal(A.getValueType()))
return SDValue();

MVT ResVT = getQDOTXResultType(A.getOperand(0).getSimpleValueType());
A = DAG.getBitcast(ResVT, A.getOperand(0));
B = DAG.getBitcast(ResVT, B.getOperand(0));
return lowerVQDOT(Opc, A, B, DL, DAG, Subtarget);
unsigned Opc;
if (A.getOpcode() == ISD::SIGN_EXTEND && B.getOpcode() == ISD::SIGN_EXTEND)
Opc = ISD::PARTIAL_REDUCE_SMLA;
else if (A.getOpcode() == ISD::ZERO_EXTEND &&
B.getOpcode() == ISD::ZERO_EXTEND)
Opc = ISD::PARTIAL_REDUCE_UMLA;
else if (A.getOpcode() == ISD::SIGN_EXTEND &&
B.getOpcode() == ISD::ZERO_EXTEND)
Opc = ISD::PARTIAL_REDUCE_SUMLA;
else if (A.getOpcode() == ISD::ZERO_EXTEND &&
B.getOpcode() == ISD::SIGN_EXTEND) {
Opc = ISD::PARTIAL_REDUCE_SUMLA;
std::swap(A, B);
} else
return SDValue();

MVT ResVT = getQDOTXResultType(OpVT.getSimpleVT());
return DAG.getNode(
Opc, DL, ResVT,
{DAG.getConstant(0, DL, ResVT), A.getOperand(0), B.getOperand(0)});
}

static SDValue performVECREDUCECombine(SDNode *N, SelectionDAG &DAG,
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -232,13 +232,13 @@ define i32 @reduce_of_sext(<16 x i8> %a) {
;
; DOT-LABEL: reduce_of_sext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
; DOT-NEXT: lui a0, 4112
; DOT-NEXT: addi a0, a0, 257
; DOT-NEXT: vqdot.vx v9, v8, a0
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: vqdot.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v9, v8
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
Expand All @@ -259,13 +259,13 @@ define i32 @reduce_of_zext(<16 x i8> %a) {
;
; DOT-LABEL: reduce_of_zext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 1
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv.v.i v9, 0
; DOT-NEXT: lui a0, 4112
; DOT-NEXT: addi a0, a0, 257
; DOT-NEXT: vqdotu.vx v9, v8, a0
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: vqdotu.vv v10, v8, v9
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v9, v8
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/rvv/zvqdotq-sdnode.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -232,13 +232,13 @@ define i32 @reduce_of_sext(<vscale x 16 x i8> %a) {
;
; DOT-LABEL: reduce_of_sext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: lui a0, 4112
; DOT-NEXT: addi a0, a0, 257
; DOT-NEXT: vqdot.vx v10, v8, a0
; DOT-NEXT: vmv.v.i v12, 0
; DOT-NEXT: vqdot.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
Expand All @@ -259,13 +259,13 @@ define i32 @reduce_of_zext(<vscale x 16 x i8> %a) {
;
; DOT-LABEL: reduce_of_zext:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 1
; DOT-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; DOT-NEXT: vmv.v.i v10, 0
; DOT-NEXT: lui a0, 4112
; DOT-NEXT: addi a0, a0, 257
; DOT-NEXT: vqdotu.vx v10, v8, a0
; DOT-NEXT: vmv.v.i v12, 0
; DOT-NEXT: vqdotu.vv v12, v8, v10
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vredsum.vs v8, v10, v8
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
Expand Down