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[ARM] Handle roundeven for MVE. #142557

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Merged
merged 1 commit into from
Jun 8, 2025
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[ARM] Handle roundeven for MVE. #142557

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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/arm_mve.td
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Original file line number Diff line number Diff line change
Expand Up @@ -710,7 +710,7 @@ defm vrndmq: vrnd<IRIntBase<"floor", [Vector]>, "m">;
defm vrndpq: vrnd<IRIntBase<"ceil", [Vector]>, "p">;
defm vrndaq: vrnd<IRIntBase<"round", [Vector]>, "a">;
defm vrndxq: vrnd<IRIntBase<"rint", [Vector]>, "x">;
defm vrndnq: vrnd<IRInt<"vrintn", [Vector]>, "n">;
defm vrndnq: vrnd<IRIntBase<"roundeven", [Vector]>, "n">;

multiclass compare_with_pred<string condname, dag arguments,
dag cmp, string suffix> {
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4 changes: 2 additions & 2 deletions clang/test/CodeGen/arm-mve-intrinsics/vrnd.c
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Expand Up @@ -148,7 +148,7 @@ float32x4_t test_vrndxq_f32(float32x4_t a)

// CHECK-LABEL: @test_vrndnq_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vrintn.v8f16(<8 x half> [[A:%.*]])
// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.roundeven.v8f16(<8 x half> [[A:%.*]])
// CHECK-NEXT: ret <8 x half> [[TMP0]]
//
float16x8_t test_vrndnq_f16(float16x8_t a)
Expand All @@ -162,7 +162,7 @@ float16x8_t test_vrndnq_f16(float16x8_t a)

// CHECK-LABEL: @test_vrndnq_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vrintn.v4f32(<4 x float> [[A:%.*]])
// CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> [[A:%.*]])
// CHECK-NEXT: ret <4 x float> [[TMP0]]
//
float32x4_t test_vrndnq_f32(float32x4_t a)
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2 changes: 0 additions & 2 deletions llvm/include/llvm/IR/IntrinsicsARM.td
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Expand Up @@ -1306,8 +1306,6 @@ foreach suffix = ["a","n","p","m"] in {
[llvm_anyvector_ty /* input */], LLVMMatchType<0>, llvm_anyvector_ty>;
}

def int_arm_mve_vrintn: DefaultAttrsIntrinsic<
[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
def int_arm_mve_vcls: DefaultAttrsIntrinsic<
[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;

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6 changes: 6 additions & 0 deletions llvm/lib/IR/AutoUpgrade.cpp
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Expand Up @@ -767,6 +767,12 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
return false; // Not 'arm.mve.vctp64'.
}

if (Name.starts_with("vrintn.v")) {
NewFn = Intrinsic::getOrInsertDeclaration(
F->getParent(), Intrinsic::roundeven, F->arg_begin()->getType());
return true;
}

// These too are changed to accept a v2i1 instead of the old v4i1.
if (Name.consume_back(".v4i1")) {
// 'arm.mve.*.v4i1'.
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2 changes: 1 addition & 1 deletion llvm/lib/Target/ARM/ARMInstrMVE.td
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Expand Up @@ -3527,7 +3527,7 @@ multiclass MVE_VRINT_m<MVEVectorVTInfo VTI, string suffix, bits<3> opcode,
}

multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> {
defm N : MVE_VRINT_m<VTI, "n", 0b000, int_arm_mve_vrintn>;
defm N : MVE_VRINT_m<VTI, "n", 0b000, froundeven>;
defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>;
defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>;
defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>;
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89 changes: 71 additions & 18 deletions llvm/test/CodeGen/Thumb2/mve-frint.ll
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Expand Up @@ -424,21 +424,74 @@ entry:
ret <2 x double> %0
}

declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
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These removed declarations don't seem related to the rest of the patch. Were they already redundant and you just noticed it in passing?

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Yep - they are not necessary any more for intrinsics, since https://discourse.llvm.org/t/recent-improvements-to-the-ir-parser/77366.

It felt cleaner to remove the definitions, as opposed to add the new roundeven calls or leave them inconsistent.

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Great!

declare <4 x float> @llvm.trunc.v4f32(<4 x float>)
declare <4 x float> @llvm.rint.v4f32(<4 x float>)
declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>)
declare <4 x float> @llvm.floor.v4f32(<4 x float>)
declare <4 x float> @llvm.round.v4f32(<4 x float>)
declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
declare <8 x half> @llvm.trunc.v8f16(<8 x half>)
declare <8 x half> @llvm.rint.v8f16(<8 x half>)
declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>)
declare <8 x half> @llvm.floor.v8f16(<8 x half>)
declare <8 x half> @llvm.round.v8f16(<8 x half>)
declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
declare <2 x double> @llvm.rint.v2f64(<2 x double>)
declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>)
declare <2 x double> @llvm.floor.v2f64(<2 x double>)
declare <2 x double> @llvm.round.v2f64(<2 x double>)
define arm_aapcs_vfpcc <4 x float> @froundeven_float32_t(<4 x float> %src) {
; CHECK-MVE-LABEL: froundeven_float32_t:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vrintn.f32 s3, s3
; CHECK-MVE-NEXT: vrintn.f32 s2, s2
; CHECK-MVE-NEXT: vrintn.f32 s1, s1
; CHECK-MVE-NEXT: vrintn.f32 s0, s0
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: froundeven_float32_t:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintn.f32 q0, q0
; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = call fast <4 x float> @llvm.roundeven.v4f32(<4 x float> %src)
ret <4 x float> %0
}

define arm_aapcs_vfpcc <8 x half> @froundeven_float16_t(<8 x half> %src) {
; CHECK-MVE-LABEL: froundeven_float16_t:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s4, s0
; CHECK-MVE-NEXT: vrintn.f16 s0, s0
; CHECK-MVE-NEXT: vrintn.f16 s4, s4
; CHECK-MVE-NEXT: vins.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vrintn.f16 s4, s4
; CHECK-MVE-NEXT: vrintn.f16 s1, s1
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vrintn.f16 s4, s4
; CHECK-MVE-NEXT: vrintn.f16 s2, s2
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vrintn.f16 s4, s4
; CHECK-MVE-NEXT: vrintn.f16 s3, s3
; CHECK-MVE-NEXT: vins.f16 s3, s4
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: froundeven_float16_t:
; CHECK-MVEFP: @ %bb.0: @ %entry
; CHECK-MVEFP-NEXT: vrintn.f16 q0, q0
; CHECK-MVEFP-NEXT: bx lr
entry:
%0 = call fast <8 x half> @llvm.roundeven.v8f16(<8 x half> %src)
ret <8 x half> %0
}

define arm_aapcs_vfpcc <2 x double> @froundeven_float64_t(<2 x double> %src) {
; CHECK-LABEL: froundeven_float64_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, r1, d9
; CHECK-NEXT: bl roundeven
; CHECK-NEXT: vmov r2, r3, d8
; CHECK-NEXT: vmov d9, r0, r1
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: bl roundeven
; CHECK-NEXT: vmov d8, r0, r1
; CHECK-NEXT: vmov q0, q4
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r7, pc}
entry:
%0 = call fast <2 x double> @llvm.roundeven.v2f64(<2 x double> %src)
ret <2 x double> %0
}
2 changes: 2 additions & 0 deletions llvm/test/CodeGen/Thumb2/mve-intrinsics/vrintn.ll
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@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s

; The llvm.arm.mve.vrintn should auto-upgrade to llvm.roundeven, which are selected to vrintn.

define arm_aapcs_vfpcc <8 x half> @test_vrndnq_f16(<8 x half> %a) {
; CHECK-LABEL: test_vrndnq_f16:
; CHECK: @ %bb.0: @ %entry
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