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[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR #142604

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Merged
merged 3 commits into from
Jun 19, 2025
Merged

[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR #142604

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dd6c6eb
[AMDGPU] New RegBankSelect: Add rules for `G_PTRTOINT` and `G_INTTOPTR`
Pierre-vh Jun 3, 2025
d1a7713
clang-format
Pierre-vh Jun 3, 2025
2786f2c
use same check line for tests
Pierre-vh Jun 4, 2025
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16 changes: 15 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -718,7 +718,21 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivP1}, {{VgprP1}, {VgprP1, Vgpr64}}})
.Any({{DivP0}, {{VgprP0}, {VgprP0, Vgpr64}}});

addRulesForGOpcs({G_INTTOPTR}).Any({{UniP4}, {{SgprP4}, {Sgpr64}}});
addRulesForGOpcs({G_INTTOPTR})
.Any({{UniPtr32}, {{SgprPtr32}, {Sgpr32}}})
.Any({{DivPtr32}, {{VgprPtr32}, {Vgpr32}}})
.Any({{UniPtr64}, {{SgprPtr64}, {Sgpr64}}})
.Any({{DivPtr64}, {{VgprPtr64}, {Vgpr64}}})
.Any({{UniPtr128}, {{SgprPtr128}, {Sgpr128}}})
.Any({{DivPtr128}, {{VgprPtr128}, {Vgpr128}}});

addRulesForGOpcs({G_PTRTOINT})
.Any({{UniS32}, {{Sgpr32}, {SgprPtr32}}})
.Any({{DivS32}, {{Vgpr32}, {VgprPtr32}}})
.Any({{UniS64}, {{Sgpr64}, {SgprPtr64}}})
.Any({{DivS64}, {{Vgpr64}, {VgprPtr64}}})
.Any({{UniS128}, {{Sgpr128}, {SgprPtr128}}})
.Any({{DivS128}, {{Vgpr128}, {VgprPtr128}}});

addRulesForGOpcs({G_ABS}, Standard).Uni(S16, {{Sgpr32Trunc}, {Sgpr32SExt}});

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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
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@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: inttoptr_s_p0
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
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Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: ptrtoint_s_p0
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