[NFC][AMDGPU] Add lit tests for FMA combining with freeze and nnan variants #142628
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-llvm-selectiondag @llvm/pr-subscribers-backend-amdgpu Author: Harrison Hao (harrisonGPU) ChangesAfter this PR #142345, combining Closes: #141622 Full diff: https://github.com/llvm/llvm-project/pull/142628.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
new file mode 100644
index 0000000000000..dbf5636ae03ed
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fold-freeze-fmul-to-fma.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
+
+define float @fma_from_freeze_mul_add_left(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_left:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_left_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_left_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_right(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_right:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_add_right_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_add_right_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %add = fadd reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %add
+}
+
+define float @fma_from_freeze_mul_sub_left(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_left:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, v0, v1, -1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_left_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_left_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_add_f32_e32 v0, -1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nnan nsz arcp contract afn float %mul.fr, 1.000000e+00
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_right(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_right:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_fma_f32 v0, -v0, v1, 1.0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %sub
+}
+
+define float @fma_from_freeze_mul_sub_right_with_nnan(float %x, float %y) {
+; CHECK-LABEL: fma_from_freeze_mul_sub_right_with_nnan:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_mul_f32_e32 v0, v0, v1
+; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; CHECK-NEXT: v_sub_f32_e32 v0, 1.0, v0
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+ %mul = fmul reassoc nnan nsz arcp contract afn float %x, %y
+ %mul.fr = freeze float %mul
+ %sub = fsub reassoc nnan nsz arcp contract afn float 1.000000e+00, %mul.fr
+ ret float %sub
+}
|
harrisonGPU
added
llvm:SelectionDAG
shiltian
reviewed
Jun 3, 2025
Thanks - but making this work in the presence of ninf and nnan is pretty important too. |
I will implement it in this PR #142250 |
harrisonGPU
changed the title
arsenm
reviewed
Jun 4, 2025
arsenm
approved these changes
Jun 4, 2025
harrisonGPU
force-pushed
the
dag-fold-test
branch
from
c2626dc to
9e6d5f8
Compare
rorth
pushed a commit
to rorth/llvm-project
that referenced
this pull request
Jun 11, 2025
…riants (llvm#142628) `freeze` on `fmul` (without `nnan`) followed by `fadd` or `fsub` into a single `fma` is supported. This patch adds lit tests to verify the optimization behavior for both nnan and non-nnan variants.
DhruvSrivastavaX
pushed a commit
to DhruvSrivastavaX/lldb-for-aix
that referenced
this pull request
Jun 12, 2025
…riants (llvm#142628) `freeze` on `fmul` (without `nnan`) followed by `fadd` or `fsub` into a single `fma` is supported. This patch adds lit tests to verify the optimization behavior for both nnan and non-nnan variants.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
After this PR #142345, combining
freezeonfmul(withoutnnan) followed byfaddorfsubinto a singlefmais supported.This patch adds lit tests to verify the optimization behavior for both nnan
and non-nnan variants.