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[X86] getIntImmCostInst - recognise i64 ICMP EQ/NE special cases #142812

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Merged
merged 3 commits into from
Jun 6, 2025
Merged

[X86] getIntImmCostInst - recognise i64 ICMP EQ/NE special cases #142812

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[X86] getIntImmCostInst - recognise i64 ICMP EQ/NE special cases
RKSimon Jun 4, 2025
ad26bbe
Merge branch 'main' into x86-immcost-icmp-eq64
RKSimon Jun 5, 2025
5a8a8ff
Merge branch 'main' into x86-immcost-icmp-eq64
RKSimon Jun 6, 2025
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11 changes: 9 additions & 2 deletions llvm/lib/Target/X86/X86TargetTransformInfo.cpp
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Expand Up @@ -5993,12 +5993,19 @@ InstructionCost X86TTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
// This is an imperfect hack to prevent constant hoisting of
// compares that might be trying to check if a 64-bit value fits in
// 32-bits. The backend can optimize these cases using a right shift by 32.
// Ideally we would check the compare predicate here. There also other
// similar immediates the backend can use shifts for.
// There are other predicates and immediates the backend can use shifts for.
if (Idx == 1 && ImmBitWidth == 64) {
uint64_t ImmVal = Imm.getZExtValue();
if (ImmVal == 0x100000000ULL || ImmVal == 0xffffffff)
return TTI::TCC_Free;

if (auto *Cmp = dyn_cast_or_null<CmpInst>(Inst)) {
if (Cmp->isEquality()) {
KnownBits Known = computeKnownBits(Cmp->getOperand(0), DL);
if (Known.countMinTrailingZeros() >= 32)
return TTI::TCC_Free;
}
}
}
ImmIdx = 1;
break;
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/X86/pr142513.ll
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Expand Up @@ -21,8 +21,7 @@ define i64 @foo(i64 %x) {
; X64-NEXT: cmpl $65509, %edi # imm = 0xFFE5
; X64-NEXT: je .LBB0_1
; X64-NEXT: # %bb.2: # %if.end
; X64-NEXT: movabsq $9219572124669181952, %rax # imm = 0x7FF2800000000000
; X64-NEXT: addq $3, %rax
; X64-NEXT: movabsq $9219572124669181955, %rax # imm = 0x7FF2800000000003
; X64-NEXT: retq
; X64-NEXT: .LBB0_1: # %if.then
entry:
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19 changes: 7 additions & 12 deletions llvm/test/CodeGen/X86/pr62145.ll
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Expand Up @@ -5,41 +5,36 @@
define void @f(i64 %a, i64 %b) nounwind {
; X86-LABEL: f:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl $-65536, %ebx # imm = 0xFFFF0000
; X86-NEXT: movl $-589824, %edi # imm = 0xFFF70000
; X86-NEXT: movl $-65536, %edi # imm = 0xFFFF0000
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This only has 16 trailing zeros. How it's affected?

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ConstantHoisting occurs before DAG+legalisation as a pre-codegen pass, where its still a i64

; X86-NEXT: cmpl $65527, %eax # imm = 0xFFF7
; X86-NEXT: jne .LBB0_2
; X86-NEXT: # %bb.1: # %if.then
; X86-NEXT: calll ext1@PLT
; X86-NEXT: .LBB0_2: # %if.end
; X86-NEXT: calll ext2@PLT
; X86-NEXT: andl %ebx, %esi
; X86-NEXT: xorl %edi, %esi
; X86-NEXT: andl %edi, %esi
; X86-NEXT: cmpl $-589824, %esi # imm = 0xFFF70000
; X86-NEXT: jne .LBB0_3
; X86-NEXT: # %bb.4: # %if.then2
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx
; X86-NEXT: jmp ext1@PLT # TAILCALL
; X86-NEXT: .LBB0_3: # %if.end3
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx
; X86-NEXT: retl
;
; X64-LABEL: f:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %r15
; X64-NEXT: pushq %r14
; X64-NEXT: pushq %rbx
; X64-NEXT: pushq %rax
; X64-NEXT: movq %rsi, %rbx
; X64-NEXT: movabsq $-281474976710656, %r14 # imm = 0xFFFF000000000000
; X64-NEXT: movabsq $-2533274790395904, %r15 # imm = 0xFFF7000000000000
; X64-NEXT: shrq $48, %rdi
; X64-NEXT: cmpl $65527, %edi # imm = 0xFFF7
; X64-NEXT: jne .LBB0_2
Expand All @@ -48,17 +43,17 @@ define void @f(i64 %a, i64 %b) nounwind {
; X64-NEXT: .LBB0_2: # %if.end
; X64-NEXT: callq ext2@PLT
; X64-NEXT: andq %r14, %rbx
; X64-NEXT: cmpq %r15, %rbx
; X64-NEXT: movabsq $-2533274790395904, %rax # imm = 0xFFF7000000000000
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Both code and test changes look good. But I don't understand the logic. we don't compare 0xFFF7000000000000 and the sink is good no matter it has 32 trailing zeros or not.

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this one is annoying - it now stops the hoist because the other icmp using -2533274790395904 is correctly recognized as simplifying to srl+icmp_i32 - but for this one, at DAG stage per-block valuetracking can't tell %shr.mask.i4 is zero in the lower bits (because the -281474976710656 mask is still hoisted), so it still performs the icmp_i64.

; X64-NEXT: addq $8, %rsp
; X64-NEXT: cmpq %rax, %rbx
; X64-NEXT: jne .LBB0_3
; X64-NEXT: # %bb.4: # %if.then2
; X64-NEXT: popq %rbx
; X64-NEXT: popq %r14
; X64-NEXT: popq %r15
; X64-NEXT: jmp ext1@PLT # TAILCALL
; X64-NEXT: .LBB0_3: # %if.end3
; X64-NEXT: popq %rbx
; X64-NEXT: popq %r14
; X64-NEXT: popq %r15
; X64-NEXT: retq
entry:
%shr.mask.i = and i64 %a, -281474976710656
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