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Merged
merged 2 commits into from
Jun 10, 2025
Merged

[llvm][RISCV] Handle required features of intrinsic correctly #143062

merged 2 commits into from
Jun 10, 2025

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4vtomat
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@4vtomat 4vtomat commented Jun 6, 2025 •
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Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.

This should fix
56592, 134962 and 121603

@4vtomat
[llvm][RISCV] Handle required features of intrinsic correctly
fed5d31 
Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.
@llvmbot llvmbot added clang Clang issues not falling into any other category backend:RISC-V clang:frontend Language frontend issues, e.g. anything involving "Sema" labels Jun 6, 2025
@llvmbot
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llvmbot commented Jun 6, 2025

@llvm/pr-subscribers-clang

Author: Brandon Wu (4vtomat)

Changes

Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.

Patch is 76.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/143062.diff

13 Files Affected:

  • (modified) clang/include/clang/Basic/riscv_andes_vector.td (+2-2)
  • (modified) clang/include/clang/Basic/riscv_sifive_vector.td (+5-5)
  • (modified) clang/include/clang/Basic/riscv_vector.td (+120-128)
  • (modified) clang/include/clang/Basic/riscv_vector_common.td (+19-19)
  • (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+1-47)
  • (modified) clang/lib/Sema/SemaRISCV.cpp (+26-34)
  • (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+1-43)
  • (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (+1-1)
  • (modified) clang/test/Sema/rvv-required-features-invalid.c (+23-14)
  • (modified) clang/test/Sema/zvk-invalid-features.c (+29-29)
  • (modified) clang/test/Sema/zvk-invalid-zvknha.c (+4-4)
  • (modified) clang/test/Sema/zvk-target-attributes.c (+24)
  • (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+7-29)
diff --git a/clang/include/clang/Basic/riscv_andes_vector.td b/clang/include/clang/Basic/riscv_andes_vector.td
index 1498ce2dcdf9e..01019cf86d6e3 100644
--- a/clang/include/clang/Basic/riscv_andes_vector.td
+++ b/clang/include/clang/Basic/riscv_andes_vector.td
@@ -30,7 +30,7 @@ multiclass RVVFPMAD {
   }
 }
 
-let RequiredFeatures = ["Xandesvpackfph"],
+let RequiredFeatures = ["xandesvpackfph"],
     UnMaskedPolicyScheme = HasPassthruOperand in {
 let ManualCodegen = [{
   {
@@ -86,7 +86,7 @@ let ManualCodegen = [{
 
 multiclass RVVD4DOT<list<list<string>> i_suffixes_prototypes,
                     list<list<string>> l_suffixes_prototypes> {
-  let RequiredFeatures = ["Xandesvdot"],
+  let RequiredFeatures = ["xandesvdot"],
       UnMaskedPolicyScheme = HasPolicyOperand,
       HasMaskedOffOperand = false,
       Log2LMUL = [-1, 0, 1, 2, 3],
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td
index f7996f362378a..772fd3ef4201f 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -50,7 +50,7 @@ multiclass RVVVCIXBuiltinSet<list<string> range, string prototype,
                              string suffix = "Uv"> {
   foreach r = range in
     let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
-                               ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
+                               ["xsfvcp", "64bit"], ["xsfvcp"]) in
       defm : VCIXBuiltinSet<NAME, NAME, suffix, prototype, r, intrinsic_types>;
 }
 
@@ -126,7 +126,7 @@ multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_ra
 }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvqmaccdod"] in {
+  let RequiredFeatures = ["xsfvqmaccdod"] in {
     defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
     defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
     defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
@@ -134,7 +134,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvqmaccqoq"] in {
+  let RequiredFeatures = ["xsfvqmaccqoq"] in {
     defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
     defm sf_vqmacc_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
     defm sf_vqmaccus_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
@@ -142,10 +142,10 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvfwmaccqqq"] in
+  let RequiredFeatures = ["xsfvfwmaccqqq"] in
     defm sf_vfwmacc_4x4x4 : RVVVFWMACCBuiltinSet<[["", "Fw", "FwFwSvv"]]>;
 
-let UnMaskedPolicyScheme = HasPassthruOperand, RequiredFeatures = ["Xsfvfnrclipxfqf"] in {
+let UnMaskedPolicyScheme = HasPassthruOperand, RequiredFeatures = ["xsfvfnrclipxfqf"] in {
 let ManualCodegen = [{
   {
     // LLVM intrinsic
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index bff8699463c43..3e22bfb330af6 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,8 +117,8 @@ multiclass RVVIndexedLoad<string op> {
         defvar eew = eew_list[0];
         defvar eew_type = eew_list[1];
         let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)) in {
           def: RVVOutOp0Op1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
             if !not(IsFloat<type>.val) then {
@@ -129,9 +129,9 @@ multiclass RVVIndexedLoad<string op> {
       defvar eew64 = "64";
       defvar eew64_type = "(Log2EEW:6)";
       let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
-                                                 ["RV64"])) in {
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin", "64bit"],
+                                 !if(!eq(type, "y"), ["zvfbfmin", "64bit"],
+                                                 ["64bit"])) in {
           def: RVVOutOp0Op1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
             if !not(IsFloat<type>.val) then {
               def: RVVOutOp0Op1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -224,8 +224,8 @@ multiclass RVVIndexedStore<string op> {
           defvar eew = eew_list[0];
           defvar eew_type = eew_list[1];
           let Name = op # eew  # "_v", IRName = op, MaskedIRName = op # "_mask",
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin"],
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                 !if(!eq(type, "y"), ["zvfbfmin"],
                                                  []<string>)) in  {
             def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
             if !not(IsFloat<type>.val) then {
@@ -236,9 +236,9 @@ multiclass RVVIndexedStore<string op> {
         defvar eew64 = "64";
         defvar eew64_type = "(Log2EEW:6)";
         let Name = op # eew64  # "_v", IRName = op, MaskedIRName = op # "_mask",
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
-                                                   ["RV64"])) in  {
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin", "64bit"],
+                                   !if(!eq(type, "y"), ["zvfbfmin", "64bit"],
+                                                   ["64bit"])) in  {
           def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
@@ -362,11 +362,11 @@ multiclass RVVNonTupleVCreateBuiltin<int dst_lmul, list<int> src_lmul_list> {
     def vcreate # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                              dst_v # src_s,
                                              "csilfd">;
-    let RequiredFeatures = ["Zvfhmin"] in
+    let RequiredFeatures = ["zvfhmin"] in
       def vcreate_h # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                                  dst_v # src_s,
                                                  "x", dst_v>;
-    let RequiredFeatures = ["Zvfbfmin"] in
+    let RequiredFeatures = ["zvfbfmin"] in
       def vcreate_bf16 # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                                     dst_v # src_s,
                                                     "y", dst_v>;
@@ -689,9 +689,9 @@ let HasBuiltinAlias = false,
 def vlm: RVVVLEMaskBuiltin;
 defm vle8: RVVVLEBuiltin<["c"]>;
 defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vle16_v", RequiredFeatures = ["zvfhmin"] in
   defm vle16_h: RVVVLEBuiltin<["x"]>;
-let Name = "vle16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vle16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vle16_bf16 : RVVVLEBuiltin<["y"]>;
 defm vle32: RVVVLEBuiltin<["i","f"]>;
 defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -699,9 +699,9 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
 def vsm : RVVVSEMaskBuiltin;
 defm vse8 : RVVVSEBuiltin<["c"]>;
 defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vse16_h: RVVVSEBuiltin<["x"]>;
-let Name = "vse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vse16_bf16: RVVVSEBuiltin<["y"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -709,18 +709,18 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
 // 7.5. Vector Strided Instructions
 defm vlse8: RVVVLSEBuiltin<["c"]>;
 defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vlse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vlse16_h: RVVVLSEBuiltin<["x"]>;
-let Name = "vlse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vlse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vlse16_bf16: RVVVLSEBuiltin<["y"]>;
 defm vlse32: RVVVLSEBuiltin<["i","f"]>;
 defm vlse64: RVVVLSEBuiltin<["l","d"]>;
 
 defm vsse8 : RVVVSSEBuiltin<["c"]>;
 defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vsse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vsse16_h: RVVVSSEBuiltin<["x"]>;
-let Name = "vsse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vsse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vsse16_bf: RVVVSSEBuiltin<["y"]>;
 defm vsse32: RVVVSSEBuiltin<["i","f"]>;
 defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -735,9 +735,9 @@ defm : RVVIndexedStore<"vsoxei">;
 // 7.7. Unit-stride Fault-Only-First Loads
 defm vle8ff: RVVVLEFFBuiltin<["c"]>;
 defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vle16ff_v", RequiredFeatures = ["zvfhmin"] in
   defm vle16ff: RVVVLEFFBuiltin<["x"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vle16ff_v", RequiredFeatures = ["zvfbfmin"] in
   defm vle16ff: RVVVLEFFBuiltin<["y"]>;
 defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
 defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -757,8 +757,8 @@ multiclass RVVUnitStridedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -824,8 +824,8 @@ multiclass RVVUnitStridedSegStoreTuple<string op> {
           MaskedIRName = op # nf # "_mask",
           NF = nf,
           HasMaskedOffOperand = false,
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin"],
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                 !if(!eq(type, "y"), ["zvfbfmin"],
                                                  []<string>)),
           ManualCodegen = [{
     {
@@ -878,8 +878,8 @@ multiclass RVVUnitStridedSegLoadFFTuple<string op> {
             IRName = op # nf # "ff",
             MaskedIRName = op # nf # "ff_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -954,8 +954,8 @@ multiclass RVVStridedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1023,8 +1023,8 @@ multiclass RVVStridedSegStoreTuple<string op> {
             NF = nf,
             HasMaskedOffOperand = false,
             MaskedPolicyScheme = NonePolicy,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1073,8 +1073,8 @@ multiclass RVVIndexedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1142,8 +1142,8 @@ multiclass RVVIndexedSegStoreTuple<string op> {
             NF = nf,
             HasMaskedOffOperand = false,
             MaskedPolicyScheme = NonePolicy,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1387,10 +1387,10 @@ let HasMasked = false,
                                    [["v", "Uv", "UvUv"]]>;
     defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd",
                                    [["v", "v", "vv"]]>;
-    let RequiredFeatures = ["Zvfhmin"] in
+    let RequiredFeatures = ["zvfhmin"] in
       defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
                                     [["v", "v", "vv"]]>;
-    let RequiredFeatures = ["Zvfbfmin"] in
+    let RequiredFeatures = ["zvfbfmin"] in
       defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
                                     [["v", "v", "vv"]]>;
   let SupportOverloading = false in
@@ -1655,7 +1655,7 @@ let ManualCodegen = [{
       defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
                                            [["vv", "w", "wvvu"],
                                             ["vf", "w", "wveu"]]>;
-      let RequiredFeatures = ["Zvfh"] in
+      let RequiredFeatures = ["zvfh"] in
         defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
                                              [["vv", "w", "wvvu"],
                                               ["vf", "w", "wveu"]]>;
@@ -1671,7 +1671,7 @@ let ManualCodegen = [{
     defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
                                          [["vv", "w", "wvv"],
                                           ["vf", "w", "wve"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
                                            [["vv", "w", "wvv"],
                                             ["vf", "w", "wve"]]>;
@@ -1786,7 +1786,7 @@ let ManualCodegen = [{
 
     // Vector BF16 widening multiply-accumulate
     let Log2LMUL = [-2, -1, 0, 1, 2],
-        RequiredFeatures = ["Zvfbfwma"],
+        RequiredFeatures = ["zvfbfwma"],
         HasMaskedOffOperand = false in
     defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
                                               [["vv", "Fw", "FwFwvvu"],
@@ -1800,7 +1800,7 @@ let ManualCodegen = [{
 
   // Vector BF16 widening multiply-accumulate
   let Log2LMUL = [-2, -1, 0, 1, 2],
-      RequiredFeatures = ["Zvfbfwma"],
+      RequiredFeatures = ["zvfbfwma"],
       HasMaskedOffOperand = false in
   defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
                                             [["vv", "Fw", "FwFwvv"],
@@ -1856,28 +1856,28 @@ let ManualCodegen = [{
   let HasFRMRoundModeOp = 1 in {
     // 13.8. Vector Floating-Point Square-Root Instruction
     defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vvu"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vvu"]]>;
 
     // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
     defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vvu"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vvu"]]>;
   }
   // 13.8. Vector Floating-Point Square-Root Instruction
   defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vv"]]>;
 
   // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
   defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vv"]]>;
 }
 
 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
 defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "fd", [["v", "v", "vv"]]>;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "x", [["v", "v", "vv"]]>;
 
 // 13.11. Vector Floating-Point MIN/MAX Instructions
@@ -1890,10 +1890,10 @@ defm vfsgnjn : RVVFloatingBinBuiltinSet;
 defm vfsgnjx : RVVFloatingBinBuiltinSet;
 }
 defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "fd">;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "x">;
 defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "fd">;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "x">;
 
 // 13.13. Vector Floating-Point Compare Instructions
@@ -1910,7 +1910,7 @@ defm vmfge : RVVFloatingMaskOutBuiltinSet;
 // 13.14. Vector Floating-Point Classify Instruction
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vfclass : RVVOp0BuiltinSet<"vfclass", "fd", [["v", "Uv", "Uvv"]]>;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfclass : RVVOp0BuiltinSet<"vfclass", "x", [["v", "Uv", "Uvv"]]>;
 }
 
@@ -1927,15 +1927,15 @@ let HasMasked = false,
     }] in {
   defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd",
                                     [["vvm", "v", "vvvm"]]>;
-  let RequiredFeatures = ["Zvfhmin"] in
+  let RequiredFeatures = ["zvfhmin"] in
     defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
                                       [["vvm", "v", "vvvm"]]>;
-  let RequiredFeatures = ["Zvfbfmin"] in
+  let RequiredFeatures = ["zvfbfmin"] in
     defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
                                       [["vvm", "v", "vvvm"]]>;
   defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "fd",
                                      [["vfm", "v", "vvem"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "x",
                                        [["vfm", "v", "vvem"]]>;
 }
@@ -1948,7 +1948,7 @@ let HasMasked = false,
     OverloadedName = "vfmv_v" in {
   defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "fd",
                                  [["f", "v", "ve"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "x",
                                    [["f", "v", "ve"]]>;
 }
@@ -1957,12 +1957,12 @@ let HasMasked = false,
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 let OverloadedName = "vfcvt_rtz_xu" in {
   defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "fd", [["Uv", "Uvv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "x", [["Uv", "Uvv"]]>;
 }
 let OverloadedName =...
[truncated]

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llvmbot commented Jun 6, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Brandon Wu (4vtomat)

Changes

Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.

Patch is 76.92 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/143062.diff

13 Files Affected:

  • (modified) clang/include/clang/Basic/riscv_andes_vector.td (+2-2)
  • (modified) clang/include/clang/Basic/riscv_sifive_vector.td (+5-5)
  • (modified) clang/include/clang/Basic/riscv_vector.td (+120-128)
  • (modified) clang/include/clang/Basic/riscv_vector_common.td (+19-19)
  • (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+1-47)
  • (modified) clang/lib/Sema/SemaRISCV.cpp (+26-34)
  • (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+1-43)
  • (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c (+1-1)
  • (modified) clang/test/Sema/rvv-required-features-invalid.c (+23-14)
  • (modified) clang/test/Sema/zvk-invalid-features.c (+29-29)
  • (modified) clang/test/Sema/zvk-invalid-zvknha.c (+4-4)
  • (modified) clang/test/Sema/zvk-target-attributes.c (+24)
  • (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+7-29)
diff --git a/clang/include/clang/Basic/riscv_andes_vector.td b/clang/include/clang/Basic/riscv_andes_vector.td
index 1498ce2dcdf9e..01019cf86d6e3 100644
--- a/clang/include/clang/Basic/riscv_andes_vector.td
+++ b/clang/include/clang/Basic/riscv_andes_vector.td
@@ -30,7 +30,7 @@ multiclass RVVFPMAD {
   }
 }
 
-let RequiredFeatures = ["Xandesvpackfph"],
+let RequiredFeatures = ["xandesvpackfph"],
     UnMaskedPolicyScheme = HasPassthruOperand in {
 let ManualCodegen = [{
   {
@@ -86,7 +86,7 @@ let ManualCodegen = [{
 
 multiclass RVVD4DOT<list<list<string>> i_suffixes_prototypes,
                     list<list<string>> l_suffixes_prototypes> {
-  let RequiredFeatures = ["Xandesvdot"],
+  let RequiredFeatures = ["xandesvdot"],
       UnMaskedPolicyScheme = HasPolicyOperand,
       HasMaskedOffOperand = false,
       Log2LMUL = [-1, 0, 1, 2, 3],
diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td
index f7996f362378a..772fd3ef4201f 100644
--- a/clang/include/clang/Basic/riscv_sifive_vector.td
+++ b/clang/include/clang/Basic/riscv_sifive_vector.td
@@ -50,7 +50,7 @@ multiclass RVVVCIXBuiltinSet<list<string> range, string prototype,
                              string suffix = "Uv"> {
   foreach r = range in
     let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")),
-                               ["Xsfvcp", "RV64"], ["Xsfvcp"]) in
+                               ["xsfvcp", "64bit"], ["xsfvcp"]) in
       defm : VCIXBuiltinSet<NAME, NAME, suffix, prototype, r, intrinsic_types>;
 }
 
@@ -126,7 +126,7 @@ multiclass RVVVFNRCLIPBuiltinSet<string suffix, string prototype, string type_ra
 }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvqmaccdod"] in {
+  let RequiredFeatures = ["xsfvqmaccdod"] in {
     defm sf_vqmaccu_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
     defm sf_vqmacc_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
     defm sf_vqmaccus_2x8x2 : RVVVQMACCDODBuiltinSet<[["", "v", "vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
@@ -134,7 +134,7 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvqmaccqoq"] in {
+  let RequiredFeatures = ["xsfvqmaccqoq"] in {
     defm sf_vqmaccu_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)Uv"]]>;
     defm sf_vqmacc_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
     defm sf_vqmaccus_4x8x4 : RVVVQMACCQOQBuiltinSet<[["", "w", "ww(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
@@ -142,10 +142,10 @@ let UnMaskedPolicyScheme = HasPolicyOperand in
   }
 
 let UnMaskedPolicyScheme = HasPolicyOperand in
-  let RequiredFeatures = ["Xsfvfwmaccqqq"] in
+  let RequiredFeatures = ["xsfvfwmaccqqq"] in
     defm sf_vfwmacc_4x4x4 : RVVVFWMACCBuiltinSet<[["", "Fw", "FwFwSvv"]]>;
 
-let UnMaskedPolicyScheme = HasPassthruOperand, RequiredFeatures = ["Xsfvfnrclipxfqf"] in {
+let UnMaskedPolicyScheme = HasPassthruOperand, RequiredFeatures = ["xsfvfnrclipxfqf"] in {
 let ManualCodegen = [{
   {
     // LLVM intrinsic
diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index bff8699463c43..3e22bfb330af6 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -117,8 +117,8 @@ multiclass RVVIndexedLoad<string op> {
         defvar eew = eew_list[0];
         defvar eew_type = eew_list[1];
         let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)) in {
           def: RVVOutOp0Op1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
             if !not(IsFloat<type>.val) then {
@@ -129,9 +129,9 @@ multiclass RVVIndexedLoad<string op> {
       defvar eew64 = "64";
       defvar eew64_type = "(Log2EEW:6)";
       let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
-                                                 ["RV64"])) in {
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin", "64bit"],
+                                 !if(!eq(type, "y"), ["zvfbfmin", "64bit"],
+                                                 ["64bit"])) in {
           def: RVVOutOp0Op1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
             if !not(IsFloat<type>.val) then {
               def: RVVOutOp0Op1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -224,8 +224,8 @@ multiclass RVVIndexedStore<string op> {
           defvar eew = eew_list[0];
           defvar eew_type = eew_list[1];
           let Name = op # eew  # "_v", IRName = op, MaskedIRName = op # "_mask",
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin"],
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                 !if(!eq(type, "y"), ["zvfbfmin"],
                                                  []<string>)) in  {
             def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
             if !not(IsFloat<type>.val) then {
@@ -236,9 +236,9 @@ multiclass RVVIndexedStore<string op> {
         defvar eew64 = "64";
         defvar eew64_type = "(Log2EEW:6)";
         let Name = op # eew64  # "_v", IRName = op, MaskedIRName = op # "_mask",
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin", "RV64"],
-                                                   ["RV64"])) in  {
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin", "64bit"],
+                                   !if(!eq(type, "y"), ["zvfbfmin", "64bit"],
+                                                   ["64bit"])) in  {
           def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
           if !not(IsFloat<type>.val) then {
             def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
@@ -362,11 +362,11 @@ multiclass RVVNonTupleVCreateBuiltin<int dst_lmul, list<int> src_lmul_list> {
     def vcreate # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                              dst_v # src_s,
                                              "csilfd">;
-    let RequiredFeatures = ["Zvfhmin"] in
+    let RequiredFeatures = ["zvfhmin"] in
       def vcreate_h # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                                  dst_v # src_s,
                                                  "x", dst_v>;
-    let RequiredFeatures = ["Zvfbfmin"] in
+    let RequiredFeatures = ["zvfbfmin"] in
       def vcreate_bf16 # src_v # dst_v : RVVBuiltin<src_v # dst_v,
                                                     dst_v # src_s,
                                                     "y", dst_v>;
@@ -689,9 +689,9 @@ let HasBuiltinAlias = false,
 def vlm: RVVVLEMaskBuiltin;
 defm vle8: RVVVLEBuiltin<["c"]>;
 defm vle16: RVVVLEBuiltin<["s"]>;
-let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vle16_v", RequiredFeatures = ["zvfhmin"] in
   defm vle16_h: RVVVLEBuiltin<["x"]>;
-let Name = "vle16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vle16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vle16_bf16 : RVVVLEBuiltin<["y"]>;
 defm vle32: RVVVLEBuiltin<["i","f"]>;
 defm vle64: RVVVLEBuiltin<["l","d"]>;
@@ -699,9 +699,9 @@ defm vle64: RVVVLEBuiltin<["l","d"]>;
 def vsm : RVVVSEMaskBuiltin;
 defm vse8 : RVVVSEBuiltin<["c"]>;
 defm vse16: RVVVSEBuiltin<["s"]>;
-let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vse16_h: RVVVSEBuiltin<["x"]>;
-let Name = "vse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vse16_bf16: RVVVSEBuiltin<["y"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
@@ -709,18 +709,18 @@ defm vse64: RVVVSEBuiltin<["l","d"]>;
 // 7.5. Vector Strided Instructions
 defm vlse8: RVVVLSEBuiltin<["c"]>;
 defm vlse16: RVVVLSEBuiltin<["s"]>;
-let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vlse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vlse16_h: RVVVLSEBuiltin<["x"]>;
-let Name = "vlse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vlse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vlse16_bf16: RVVVLSEBuiltin<["y"]>;
 defm vlse32: RVVVLSEBuiltin<["i","f"]>;
 defm vlse64: RVVVLSEBuiltin<["l","d"]>;
 
 defm vsse8 : RVVVSSEBuiltin<["c"]>;
 defm vsse16: RVVVSSEBuiltin<["s"]>;
-let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vsse16_v", RequiredFeatures = ["zvfhmin"] in
   defm vsse16_h: RVVVSSEBuiltin<["x"]>;
-let Name = "vsse16_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vsse16_v", RequiredFeatures = ["zvfbfmin"] in
   defm vsse16_bf: RVVVSSEBuiltin<["y"]>;
 defm vsse32: RVVVSSEBuiltin<["i","f"]>;
 defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -735,9 +735,9 @@ defm : RVVIndexedStore<"vsoxei">;
 // 7.7. Unit-stride Fault-Only-First Loads
 defm vle8ff: RVVVLEFFBuiltin<["c"]>;
 defm vle16ff: RVVVLEFFBuiltin<["s"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
+let Name = "vle16ff_v", RequiredFeatures = ["zvfhmin"] in
   defm vle16ff: RVVVLEFFBuiltin<["x"]>;
-let Name = "vle16ff_v", RequiredFeatures = ["Zvfbfmin"] in
+let Name = "vle16ff_v", RequiredFeatures = ["zvfbfmin"] in
   defm vle16ff: RVVVLEFFBuiltin<["y"]>;
 defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
 defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -757,8 +757,8 @@ multiclass RVVUnitStridedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -824,8 +824,8 @@ multiclass RVVUnitStridedSegStoreTuple<string op> {
           MaskedIRName = op # nf # "_mask",
           NF = nf,
           HasMaskedOffOperand = false,
-          RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                 !if(!eq(type, "y"), ["Zvfbfmin"],
+          RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                 !if(!eq(type, "y"), ["zvfbfmin"],
                                                  []<string>)),
           ManualCodegen = [{
     {
@@ -878,8 +878,8 @@ multiclass RVVUnitStridedSegLoadFFTuple<string op> {
             IRName = op # nf # "ff",
             MaskedIRName = op # nf # "ff_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -954,8 +954,8 @@ multiclass RVVStridedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1023,8 +1023,8 @@ multiclass RVVStridedSegStoreTuple<string op> {
             NF = nf,
             HasMaskedOffOperand = false,
             MaskedPolicyScheme = NonePolicy,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1073,8 +1073,8 @@ multiclass RVVIndexedSegLoadTuple<string op> {
             IRName = op # nf,
             MaskedIRName = op # nf # "_mask",
             NF = nf,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1142,8 +1142,8 @@ multiclass RVVIndexedSegStoreTuple<string op> {
             NF = nf,
             HasMaskedOffOperand = false,
             MaskedPolicyScheme = NonePolicy,
-            RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
-                                   !if(!eq(type, "y"), ["Zvfbfmin"],
+            RequiredFeatures = !if(!eq(type, "x"), ["zvfhmin"],
+                                   !if(!eq(type, "y"), ["zvfbfmin"],
                                                    []<string>)),
             ManualCodegen = [{
     {
@@ -1387,10 +1387,10 @@ let HasMasked = false,
                                    [["v", "Uv", "UvUv"]]>;
     defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd",
                                    [["v", "v", "vv"]]>;
-    let RequiredFeatures = ["Zvfhmin"] in
+    let RequiredFeatures = ["zvfhmin"] in
       defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
                                     [["v", "v", "vv"]]>;
-    let RequiredFeatures = ["Zvfbfmin"] in
+    let RequiredFeatures = ["zvfbfmin"] in
       defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "y",
                                     [["v", "v", "vv"]]>;
   let SupportOverloading = false in
@@ -1655,7 +1655,7 @@ let ManualCodegen = [{
       defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
                                            [["vv", "w", "wvvu"],
                                             ["vf", "w", "wveu"]]>;
-      let RequiredFeatures = ["Zvfh"] in
+      let RequiredFeatures = ["zvfh"] in
         defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
                                              [["vv", "w", "wvvu"],
                                               ["vf", "w", "wveu"]]>;
@@ -1671,7 +1671,7 @@ let ManualCodegen = [{
     defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "f",
                                          [["vv", "w", "wvv"],
                                           ["vf", "w", "wve"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "x",
                                            [["vv", "w", "wvv"],
                                             ["vf", "w", "wve"]]>;
@@ -1786,7 +1786,7 @@ let ManualCodegen = [{
 
     // Vector BF16 widening multiply-accumulate
     let Log2LMUL = [-2, -1, 0, 1, 2],
-        RequiredFeatures = ["Zvfbfwma"],
+        RequiredFeatures = ["zvfbfwma"],
         HasMaskedOffOperand = false in
     defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
                                               [["vv", "Fw", "FwFwvvu"],
@@ -1800,7 +1800,7 @@ let ManualCodegen = [{
 
   // Vector BF16 widening multiply-accumulate
   let Log2LMUL = [-2, -1, 0, 1, 2],
-      RequiredFeatures = ["Zvfbfwma"],
+      RequiredFeatures = ["zvfbfwma"],
       HasMaskedOffOperand = false in
   defm vfwmaccbf16 : RVVOutOp1Op2BuiltinSet<"vfwmaccbf16", "y",
                                             [["vv", "Fw", "FwFwvv"],
@@ -1856,28 +1856,28 @@ let ManualCodegen = [{
   let HasFRMRoundModeOp = 1 in {
     // 13.8. Vector Floating-Point Square-Root Instruction
     defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vvu"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vvu"]]>;
 
     // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
     defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vvu"]]>;
-    let RequiredFeatures = ["Zvfh"] in
+    let RequiredFeatures = ["zvfh"] in
       defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vvu"]]>;
   }
   // 13.8. Vector Floating-Point Square-Root Instruction
   defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "fd", [["v", "v", "vv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfsqrt : RVVOutBuiltinSet<"vfsqrt", "x", [["v", "v", "vv"]]>;
 
   // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
   defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "fd", [["v", "v", "vv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfrec7 : RVVOutBuiltinSet<"vfrec7", "x", [["v", "v", "vv"]]>;
 }
 
 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
 defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "fd", [["v", "v", "vv"]]>;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfrsqrt7 : RVVOutBuiltinSet<"vfrsqrt7", "x", [["v", "v", "vv"]]>;
 
 // 13.11. Vector Floating-Point MIN/MAX Instructions
@@ -1890,10 +1890,10 @@ defm vfsgnjn : RVVFloatingBinBuiltinSet;
 defm vfsgnjx : RVVFloatingBinBuiltinSet;
 }
 defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "fd">;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "x">;
 defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "fd">;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "x">;
 
 // 13.13. Vector Floating-Point Compare Instructions
@@ -1910,7 +1910,7 @@ defm vmfge : RVVFloatingMaskOutBuiltinSet;
 // 13.14. Vector Floating-Point Classify Instruction
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 defm vfclass : RVVOp0BuiltinSet<"vfclass", "fd", [["v", "Uv", "Uvv"]]>;
-let RequiredFeatures = ["Zvfh"] in
+let RequiredFeatures = ["zvfh"] in
   defm vfclass : RVVOp0BuiltinSet<"vfclass", "x", [["v", "Uv", "Uvv"]]>;
 }
 
@@ -1927,15 +1927,15 @@ let HasMasked = false,
     }] in {
   defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd",
                                     [["vvm", "v", "vvvm"]]>;
-  let RequiredFeatures = ["Zvfhmin"] in
+  let RequiredFeatures = ["zvfhmin"] in
     defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
                                       [["vvm", "v", "vvvm"]]>;
-  let RequiredFeatures = ["Zvfbfmin"] in
+  let RequiredFeatures = ["zvfbfmin"] in
     defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "y",
                                       [["vvm", "v", "vvvm"]]>;
   defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "fd",
                                      [["vfm", "v", "vvem"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "x",
                                        [["vfm", "v", "vvem"]]>;
 }
@@ -1948,7 +1948,7 @@ let HasMasked = false,
     OverloadedName = "vfmv_v" in {
   defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "fd",
                                  [["f", "v", "ve"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm vfmv_v : RVVOutBuiltinSet<"vfmv_v_f", "x",
                                    [["f", "v", "ve"]]>;
 }
@@ -1957,12 +1957,12 @@ let HasMasked = false,
 let UnMaskedPolicyScheme = HasPassthruOperand in {
 let OverloadedName = "vfcvt_rtz_xu" in {
   defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "fd", [["Uv", "Uvv"]]>;
-  let RequiredFeatures = ["Zvfh"] in
+  let RequiredFeatures = ["zvfh"] in
     defm : RVVConvBuiltinSet<"vfcvt_rtz_xu_f_v", "x", [["Uv", "Uvv"]]>;
 }
 let OverloadedName =...
[truncated]

tclin914
tclin914 reviewed Jun 9, 2025
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topperc
topperc reviewed Jun 9, 2025
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tclin914
tclin914 approved these changes Jun 10, 2025
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LGTM

topperc
topperc approved these changes Jun 10, 2025
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LGTM

@4vtomat 4vtomat merged commit 9312d5b into llvm:main Jun 10, 2025
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rorth pushed a commit to rorth/llvm-project that referenced this pull request Jun 11, 2025
@4vtomat @rorth
[llvm][RISCV] Handle required features of intrinsic correctly (llvm#1…
d845b58 
…43062)

Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.

This should fix
[56592](llvm#56592),
[134962](llvm#134962) and
[121603](llvm#121603)
tomtor pushed a commit to tomtor/llvm-project that referenced this pull request Jun 14, 2025
@4vtomat @tomtor
[llvm][RISCV] Handle required features of intrinsic correctly (llvm#1…
da1e418 
…43062)

Current approach generates intrinsic records when users specify
corresponding required features by using command line option.
However it's not able to handle features passed by using target
attributes correctly where each function might have different
features.
This patch resolves this by generating all of intrinsic records which
carry the required features in their function declaration using
attribute and check the required extensions in CheckBuiltinFunctionCall.

This should fix
[56592](llvm#56592),
[134962](llvm#134962) and
[121603](llvm#121603)
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@tclin914 tclin914 tclin914 approved these changes

@topperc topperc topperc approved these changes

@wangpc-pp wangpc-pp wangpc-pp approved these changes

@kito-cheng kito-cheng Awaiting requested review from kito-cheng

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