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[NVPTX] Use prmt.f4e to lower pointer alignment fshr idiom #143407

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Merged
merged 1 commit into from
Jun 13, 2025
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[NVPTX] Use prmt.f4e to lower pointer alignment fshr idiom #143407

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4 changes: 4 additions & 0 deletions llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1636,6 +1636,10 @@ let hasSideEffects = false in {

}

// PRMT folding patterns
def : Pat<(fshr i32:$hi, i32:$lo, (shl i32:$amt, (i32 3))),
(PRMT_B32rrr $lo, $hi, $amt, PrmtF4E)>;


// byte extraction + signed/unsigned extension to i32.
def : Pat<(i32 (sext_inreg (bfe i32:$s, i32:$o, 8), i8)),
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21 changes: 19 additions & 2 deletions llvm/test/CodeGen/NVPTX/prmt.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -verify-machineinstrs | FileCheck %s
; RUN: %if ptxas %{ llc < %s -verify-machineinstrs | %ptxas-verify %}
; RUN: llc < %s -verify-machineinstrs -mcpu=sm_50 | FileCheck %s
; RUN: %if ptxas %{ llc < %s -verify-machineinstrs -mcpu=sm_50 | %ptxas-verify %}

target triple = "nvptx64-nvidia-cuda"

Expand Down Expand Up @@ -111,3 +111,20 @@ define i32 @test_prmt_rc16(i32 %lo, i32 %selector) {
%val = call i32 @llvm.nvvm.prmt.rc16(i32 %lo, i32 %selector)
ret i32 %val
}

define i32 @test_prmt_f4e_folding(i32 %lo, i32 %hi, i32 %ptr) {
; CHECK-LABEL: test_prmt_f4e_folding(
; CHECK: {
; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b32 %r1, [test_prmt_f4e_folding_param_0];
; CHECK-NEXT: ld.param.b32 %r2, [test_prmt_f4e_folding_param_1];
; CHECK-NEXT: ld.param.b32 %r3, [test_prmt_f4e_folding_param_2];
; CHECK-NEXT: prmt.b32.f4e %r4, %r1, %r2, %r3;
; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-NEXT: ret;
%sh_amt = shl i32 %ptr, 3
%val = call i32 @llvm.fshr.i32(i32 %hi, i32 %lo, i32 %sh_amt)
ret i32 %val
}
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