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[RISCV] Fold vmv.v.v into vleNff.v #143981

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Merged
merged 4 commits into from
Jun 13, 2025
Merged

[RISCV] Fold vmv.v.v into vleNff.v #143981

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153f149
[RISCV] Remove implicit $vl def on vleNff pseudos
lukel97 Jun 12, 2025
ec16b44
Precommit tests
lukel97 Jun 12, 2025
0b238ee
[RISCV] Fold vmv.v.v into vleNff.v
lukel97 Jun 12, 2025
5255699
Merge branch 'main' into vector-peephole/fold-vmv.v.v-vleff
lukel97 Jun 12, 2025
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7 changes: 4 additions & 3 deletions llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -611,7 +611,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {

MachineInstr *Src = MRI->getVRegDef(MI.getOperand(2).getReg());
if (!Src || Src->hasUnmodeledSideEffects() ||
Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
Src->getParent() != MI.getParent() ||
!RISCVII::isFirstDefTiedToFirstUse(Src->getDesc()) ||
!RISCVII::hasVLOp(Src->getDesc().TSFlags) ||
!RISCVII::hasVecPolicyOp(Src->getDesc().TSFlags))
Expand All @@ -622,7 +622,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
return false;

// Src needs to have the same passthru as VMV_V_V
MachineOperand &SrcPassthru = Src->getOperand(1);
MachineOperand &SrcPassthru = Src->getOperand(Src->getNumExplicitDefs());
if (SrcPassthru.getReg() != RISCV::NoRegister &&
SrcPassthru.getReg() != Passthru.getReg())
return false;
Expand All @@ -643,7 +643,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
// If Src is masked then its passthru needs to be in VRNoV0.
if (Passthru.getReg() != RISCV::NoRegister)
MRI->constrainRegClass(Passthru.getReg(),
TII->getRegClass(Src->getDesc(), 1, TRI,
TII->getRegClass(Src->getDesc(),
SrcPassthru.getOperandNo(), TRI,
*Src->getParent()->getParent()));
}

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16 changes: 16 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll
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Expand Up @@ -206,3 +206,19 @@ define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale
%b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)
ret <vscale x 1 x i64> %b
}

; Check that we can fold into vle64ff.v even if we need to move it past the
; passthru and it's safe.
define <vscale x 1 x i64> @vleff_move_past_passthru(ptr %p, ptr %q, iXLen %avl) {
; CHECK-LABEL: vleff_move_past_passthru:
; CHECK: # %bb.0:
; CHECK-NEXT: vl1re64.v v8, (a1)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, tu, ma
; CHECK-NEXT: vle64ff.v v8, (a0)
; CHECK-NEXT: ret
%a = call { <vscale x 1 x i64>, iXLen } @llvm.riscv.vleff(<vscale x 1 x i64> poison, ptr %p, iXLen %avl)
%vec = extractvalue { <vscale x 1 x i64>, iXLen } %a, 0
%passthru = load <vscale x 1 x i64>, ptr %q
%b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %vec, iXLen %avl)
ret <vscale x 1 x i64> %b
}
17 changes: 17 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir
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Expand Up @@ -135,3 +135,20 @@ body: |
%3:vrnov0 = PseudoVMV_V_V_MF2 $noreg, %2, 0, 5 /* e32 */, 0 /* tu, mu */
%7:vmv0 = COPY $v8
%6:vrnov0 = PseudoVLSE32_V_MF2_MASK %3, $noreg, $noreg, %7, 0, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 4)
...
---
name: move_vleff
body: |
bb.0:
liveins: $v8
; CHECK-LABEL: name: move_vleff
; CHECK: liveins: $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %passthru:vr = COPY $v8
; CHECK-NEXT: %x:vr, %vl:gpr = PseudoVLE32FF_V_M1 %passthru, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size, align 1)
; CHECK-NEXT: %y:gpr = ADDI $x0, 1
%x:vr, %vl:gpr = PseudoVLE32FF_V_M1 $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */ :: (load unknown-size)
%passthru:vr = COPY $v8
%y:gpr = ADDI $x0, 1
%z:vr = PseudoVMV_V_V_M1 %passthru, %x, 4, 5 /* e32 */, 0 /* tu, mu */
...
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