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[NVPTX] Attach Range attr to setmaxnreg and fence intrinsics #144120

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Jun 19, 2025
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[NVPTX] Attach Range attr to setmaxnreg and fence intrinsics #144120

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8 changes: 6 additions & 2 deletions llvm/include/llvm/IR/IntrinsicsNVVM.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1341,9 +1341,11 @@ foreach scope = ["cta", "cluster", "gpu", "sys"] in {
Intrinsic<[], [], [IntrNoCallback],
"llvm.nvvm.fence.proxy.tensormap_generic.release." # scope>;

// The imm-arg 'size' can only be 128.
def int_nvvm_fence_proxy_tensormap_generic_acquire_ # scope :
Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
[IntrNoCallback, IntrArgMemOnly, ImmArg<ArgIndex<1>>],
[IntrNoCallback, IntrArgMemOnly, ImmArg<ArgIndex<1>>,
Range<ArgIndex<1>, 128, 129>],
"llvm.nvvm.fence.proxy.tensormap_generic.acquire." # scope>;
}

Expand Down Expand Up @@ -1989,10 +1991,12 @@ def int_nvvm_is_explicit_cluster
"llvm.nvvm.is_explicit_cluster">;

// Setmaxnreg inc/dec intrinsics
// The imm-arg should be in the range: 24 <= val <= 256
foreach op = ["dec", "inc"] in
def int_nvvm_setmaxnreg_ # op # _sync_aligned_u32
: DefaultAttrsIntrinsic<[], [llvm_i32_ty],
[IntrConvergent, IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
[IntrConvergent, IntrNoMem, IntrHasSideEffects,
ImmArg<ArgIndex<0>>, Range<ArgIndex<0>, 24, 257>]>;

// Exit
def int_nvvm_exit : NVVMBuiltin,
Expand Down
10 changes: 0 additions & 10 deletions llvm/lib/IR/Verifier.cpp
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Expand Up @@ -6557,8 +6557,6 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
unsigned RegCount = cast<ConstantInt>(V)->getZExtValue();
Check(RegCount % 8 == 0,
"reg_count argument to nvvm.setmaxnreg must be in multiples of 8");
Check((RegCount >= 24 && RegCount <= 256),
"reg_count argument to nvvm.setmaxnreg must be within [24, 256]");
break;
}
case Intrinsic::experimental_convergence_entry:
Expand Down Expand Up @@ -6605,14 +6603,6 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
"llvm.threadlocal.address operand isThreadLocal() must be true");
break;
}
case Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_cta:
case Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_cluster:
case Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_gpu:
case Intrinsic::nvvm_fence_proxy_tensormap_generic_acquire_sys: {
unsigned size = cast<ConstantInt>(Call.getArgOperand(1))->getZExtValue();
Check(size == 128, " The only supported value for size operand is 128");
break;
}
};

// Verify that there aren't any unmediated control transfers between funclets.
Expand Down
17 changes: 17 additions & 0 deletions llvm/test/Verifier/NVPTX/fence-proxy.tensormap.ll
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@@ -0,0 +1,17 @@
; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s

define void @test_fence_proxy_tensormap_generic_acquire(ptr addrspace(0) %addr) {
; CHECK: immarg value 127 out of range [128, 129)
call void @llvm.nvvm.fence.proxy.tensormap_generic.acquire.cta(ptr addrspace(0) %addr, i32 127);

; CHECK: immarg value 129 out of range [128, 129)
call void @llvm.nvvm.fence.proxy.tensormap_generic.acquire.cluster(ptr addrspace(0) %addr, i32 129);

; CHECK: immarg value 127 out of range [128, 129)
call void @llvm.nvvm.fence.proxy.tensormap_generic.acquire.gpu(ptr addrspace(0) %addr, i32 127);

; CHECK: immarg value 129 out of range [128, 129)
call void @llvm.nvvm.fence.proxy.tensormap_generic.acquire.sys(ptr addrspace(0) %addr, i32 129);

ret void
}
4 changes: 3 additions & 1 deletion llvm/test/Verifier/NVPTX/setmaxnreg.ll
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Expand Up @@ -7,8 +7,10 @@ define void @test_set_maxn_reg() {
; CHECK: reg_count argument to nvvm.setmaxnreg must be in multiples of 8
call void @llvm.nvvm.setmaxnreg.inc.sync.aligned.u32(i32 95)

; CHECK: reg_count argument to nvvm.setmaxnreg must be within [24, 256]
; CHECK: immarg value 16 out of range [24, 257)
call void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 16)

; CHECK: immarg value 264 out of range [24, 257)
call void @llvm.nvvm.setmaxnreg.dec.sync.aligned.u32(i32 264)
ret void
}
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