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[PowerPC][AIX] Specify pointer info and alignment for stack store #144526

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Jun 18, 2025
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[PowerPC][AIX] Specify pointer info and alignment for stack store #144526

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4 changes: 3 additions & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7767,7 +7767,9 @@ SDValue PPCTargetLowering::LowerCall_AIX(
DAG.getConstant(VA.getLocMemOffset(), dl, StackPtr.getValueType());
PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
MemOpChains.push_back(
DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
DAG.getStore(Chain, dl, Arg, PtrOff,
MachinePointerInfo::getStack(MF, VA.getLocMemOffset()),
Subtarget.getFrameLowering()->getStackAlign()));

continue;
}
Expand Down
366 changes: 189 additions & 177 deletions llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
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176 changes: 94 additions & 82 deletions llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1012,18 +1012,22 @@ define void @call_test_stackarg_float() {
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfs 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
; ASM32PWR4-NEXT: li 10, 8
; ASM32PWR4-NEXT: lfd 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
; ASM32PWR4-NEXT: li 10, 8
; ASM32PWR4-NEXT: stfd 2, 60(1)
; ASM32PWR4-NEXT: stfd 2, 72(1)
; ASM32PWR4-NEXT: lwz 5, 76(1)
; ASM32PWR4-NEXT: lwz 11, 72(1)
; ASM32PWR4-NEXT: stw 5, 64(1)
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: stfs 1, 56(1)
; ASM32PWR4-NEXT: stw 11, 60(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
Expand Down Expand Up @@ -1126,20 +1130,24 @@ define void @call_test_stackarg_float3() {
; ASM32PWR4-NEXT: stwu 1, -80(1)
; ASM32PWR4-NEXT: lwz 3, L..C9(2) # @d
; ASM32PWR4-NEXT: stw 0, 88(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: li 5, 3
; ASM32PWR4-NEXT: li 6, 4
; ASM32PWR4-NEXT: li 7, 5
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: lfd 1, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C8(2) # @f
; ASM32PWR4-NEXT: li 8, 6
; ASM32PWR4-NEXT: li 9, 7
; ASM32PWR4-NEXT: stfd 1, 72(1)
; ASM32PWR4-NEXT: lwz 10, 72(1)
; ASM32PWR4-NEXT: lfs 2, 0(3)
; ASM32PWR4-NEXT: li 3, 1
; ASM32PWR4-NEXT: stfd 1, 64(1)
; ASM32PWR4-NEXT: lwz 4, 68(1)
; ASM32PWR4-NEXT: lwz 10, 72(1)
; ASM32PWR4-NEXT: lwz 11, 64(1)
; ASM32PWR4-NEXT: stw 4, 56(1)
; ASM32PWR4-NEXT: li 4, 2
; ASM32PWR4-NEXT: stfs 2, 60(1)
; ASM32PWR4-NEXT: stfd 1, 52(1)
; ASM32PWR4-NEXT: stw 11, 52(1)
; ASM32PWR4-NEXT: bl .test_stackarg_float3[PR]
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 80
Expand Down Expand Up @@ -1562,95 +1570,99 @@ define void @caller_fpr_stack() {
; ASM32PWR4-LABEL: caller_fpr_stack:
; ASM32PWR4: # %bb.0: # %entry
; ASM32PWR4-NEXT: mflr 0
; ASM32PWR4-NEXT: stwu 1, -144(1)
; ASM32PWR4-NEXT: stwu 1, -160(1)
; ASM32PWR4-NEXT: lwz 3, L..C19(2) # @d15
; ASM32PWR4-NEXT: lwz 4, L..C20(2) # @f14
; ASM32PWR4-NEXT: lwz 5, L..C21(2) # @f16
; ASM32PWR4-NEXT: stw 0, 152(1)
; ASM32PWR4-NEXT: lis 6, 16361
; ASM32PWR4-NEXT: ori 6, 6, 39321
; ASM32PWR4-NEXT: stw 0, 168(1)
; ASM32PWR4-NEXT: lwz 5, L..C20(2) # %const.1
; ASM32PWR4-NEXT: lwz 4, L..C21(2) # @f14
; ASM32PWR4-NEXT: lfd 0, 0(3)
; ASM32PWR4-NEXT: lwz 3, 0(4)
; ASM32PWR4-NEXT: lwz 4, 0(5)
; ASM32PWR4-NEXT: li 5, 0
; ASM32PWR4-NEXT: stw 5, 60(1)
; ASM32PWR4-NEXT: lis 5, 16352
; ASM32PWR4-NEXT: stw 5, 56(1)
; ASM32PWR4-NEXT: lis 5, 13107
; ASM32PWR4-NEXT: ori 5, 5, 13107
; ASM32PWR4-NEXT: stw 5, 68(1)
; ASM32PWR4-NEXT: lis 5, 16355
; ASM32PWR4-NEXT: ori 5, 5, 13107
; ASM32PWR4-NEXT: stw 5, 64(1)
; ASM32PWR4-NEXT: lis 5, 26214
; ASM32PWR4-NEXT: ori 5, 5, 26214
; ASM32PWR4-NEXT: stw 5, 76(1)
; ASM32PWR4-NEXT: lis 5, 16358
; ASM32PWR4-NEXT: ori 5, 5, 26214
; ASM32PWR4-NEXT: stw 5, 72(1)
; ASM32PWR4-NEXT: lis 5, -26215
; ASM32PWR4-NEXT: ori 5, 5, 39322
; ASM32PWR4-NEXT: stw 5, 84(1)
; ASM32PWR4-NEXT: stw 5, 100(1)
; ASM32PWR4-NEXT: lis 5, 16313
; ASM32PWR4-NEXT: ori 5, 5, 39321
; ASM32PWR4-NEXT: stw 5, 96(1)
; ASM32PWR4-NEXT: lis 5, -15729
; ASM32PWR4-NEXT: ori 5, 5, 23593
; ASM32PWR4-NEXT: stw 5, 108(1)
; ASM32PWR4-NEXT: lis 5, 16316
; ASM32PWR4-NEXT: ori 5, 5, 10485
; ASM32PWR4-NEXT: stw 5, 104(1)
; ASM32PWR4-NEXT: lis 5, -5243
; ASM32PWR4-NEXT: ori 5, 5, 7864
; ASM32PWR4-NEXT: stw 5, 116(1)
; ASM32PWR4-NEXT: lis 5, 16318
; ASM32PWR4-NEXT: ori 5, 5, 47185
; ASM32PWR4-NEXT: stw 6, 80(1)
; ASM32PWR4-NEXT: lis 6, -13108
; ASM32PWR4-NEXT: ori 6, 6, 52429
; ASM32PWR4-NEXT: stw 5, 112(1)
; ASM32PWR4-NEXT: lis 5, 2621
; ASM32PWR4-NEXT: ori 5, 5, 28836
; ASM32PWR4-NEXT: stw 6, 92(1)
; ASM32PWR4-NEXT: lis 6, 16364
; ASM32PWR4-NEXT: ori 6, 6, 52428
; ASM32PWR4-NEXT: stw 5, 124(1)
; ASM32PWR4-NEXT: lis 5, 16320
; ASM32PWR4-NEXT: ori 5, 5, 41943
; ASM32PWR4-NEXT: stw 6, 88(1)
; ASM32PWR4-NEXT: lwz 6, L..C22(2) # %const.0
; ASM32PWR4-NEXT: stw 5, 120(1)
; ASM32PWR4-NEXT: lwz 5, L..C23(2) # %const.1
; ASM32PWR4-NEXT: lfd 2, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C24(2) # %const.2
; ASM32PWR4-NEXT: lwz 3, L..C22(2) # @f16
; ASM32PWR4-NEXT: lwz 3, 0(3)
; ASM32PWR4-NEXT: stw 3, 140(1)
; ASM32PWR4-NEXT: li 3, 0
; ASM32PWR4-NEXT: stw 3, 60(1)
; ASM32PWR4-NEXT: lis 3, 16352
; ASM32PWR4-NEXT: stw 3, 56(1)
; ASM32PWR4-NEXT: lis 3, 13107
; ASM32PWR4-NEXT: ori 3, 3, 13107
; ASM32PWR4-NEXT: stw 3, 68(1)
; ASM32PWR4-NEXT: lis 3, 16355
; ASM32PWR4-NEXT: ori 3, 3, 13107
; ASM32PWR4-NEXT: stw 3, 64(1)
; ASM32PWR4-NEXT: lis 3, 26214
; ASM32PWR4-NEXT: ori 3, 3, 26214
; ASM32PWR4-NEXT: stw 3, 76(1)
; ASM32PWR4-NEXT: lis 3, 16358
; ASM32PWR4-NEXT: ori 3, 3, 26214
; ASM32PWR4-NEXT: stw 3, 72(1)
; ASM32PWR4-NEXT: lis 3, -26215
; ASM32PWR4-NEXT: ori 3, 3, 39322
; ASM32PWR4-NEXT: stw 3, 84(1)
; ASM32PWR4-NEXT: stw 3, 100(1)
; ASM32PWR4-NEXT: lis 3, 16313
; ASM32PWR4-NEXT: ori 3, 3, 39321
; ASM32PWR4-NEXT: stw 3, 96(1)
; ASM32PWR4-NEXT: lis 3, -15729
; ASM32PWR4-NEXT: ori 3, 3, 23593
; ASM32PWR4-NEXT: stw 3, 108(1)
; ASM32PWR4-NEXT: lis 3, 16316
; ASM32PWR4-NEXT: ori 3, 3, 10485
; ASM32PWR4-NEXT: stw 3, 104(1)
; ASM32PWR4-NEXT: lis 3, -5243
; ASM32PWR4-NEXT: ori 3, 3, 7864
; ASM32PWR4-NEXT: stw 3, 116(1)
; ASM32PWR4-NEXT: lis 3, 16318
; ASM32PWR4-NEXT: ori 3, 3, 47185
; ASM32PWR4-NEXT: stw 3, 112(1)
; ASM32PWR4-NEXT: lis 3, 2621
; ASM32PWR4-NEXT: ori 3, 3, 28836
; ASM32PWR4-NEXT: stw 3, 124(1)
; ASM32PWR4-NEXT: lis 3, 16320
; ASM32PWR4-NEXT: ori 3, 3, 41943
; ASM32PWR4-NEXT: stw 3, 120(1)
; ASM32PWR4-NEXT: lwz 3, L..C23(2) # %const.0
; ASM32PWR4-NEXT: lfd 2, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C24(2) # %const.2
; ASM32PWR4-NEXT: lfd 3, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C25(2) # %const.3
; ASM32PWR4-NEXT: lfd 4, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C26(2) # %const.4
; ASM32PWR4-NEXT: lfd 4, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C26(2) # %const.4
; ASM32PWR4-NEXT: lfd 6, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C27(2) # %const.5
; ASM32PWR4-NEXT: lfd 7, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C28(2) # %const.6
; ASM32PWR4-NEXT: lwz 4, 0(4)
; ASM32PWR4-NEXT: lfd 7, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C28(2) # %const.6
; ASM32PWR4-NEXT: lfd 8, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C29(2) # %const.7
; ASM32PWR4-NEXT: lfd 9, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C30(2) # %const.8
; ASM32PWR4-NEXT: stw 4, 128(1)
; ASM32PWR4-NEXT: lis 4, 16361
; ASM32PWR4-NEXT: ori 4, 4, 39321
; ASM32PWR4-NEXT: lfd 9, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C30(2) # %const.8
; ASM32PWR4-NEXT: lfd 1, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C31(2) # %const.9
; ASM32PWR4-NEXT: lfd 11, 0(6)
; ASM32PWR4-NEXT: lwz 6, L..C32(2) # %const.10
; ASM32PWR4-NEXT: stw 4, 80(1)
; ASM32PWR4-NEXT: lis 4, -13108
; ASM32PWR4-NEXT: fmr 10, 1
; ASM32PWR4-NEXT: ori 4, 4, 52429
; ASM32PWR4-NEXT: lfd 11, 0(3)
; ASM32PWR4-NEXT: lwz 3, L..C32(2) # %const.10
; ASM32PWR4-NEXT: lfd 12, 0(5)
; ASM32PWR4-NEXT: lwz 5, L..C33(2) # %const.11
; ASM32PWR4-NEXT: lfd 13, 0(6)
; ASM32PWR4-NEXT: stw 4, 92(1)
; ASM32PWR4-NEXT: lis 4, 16364
; ASM32PWR4-NEXT: ori 4, 4, 52428
; ASM32PWR4-NEXT: stfd 0, 152(1)
; ASM32PWR4-NEXT: stw 4, 88(1)
; ASM32PWR4-NEXT: lwz 4, 156(1)
; ASM32PWR4-NEXT: lfd 13, 0(3)
; ASM32PWR4-NEXT: lfs 5, 0(5)
; ASM32PWR4-NEXT: stfd 0, 132(1)
; ASM32PWR4-NEXT: stw 4, 140(1)
; ASM32PWR4-NEXT: stw 3, 128(1)
; ASM32PWR4-NEXT: lwz 3, 152(1)
; ASM32PWR4-NEXT: stw 4, 136(1)
; ASM32PWR4-NEXT: stw 3, 132(1)
; ASM32PWR4-NEXT: bl .test_fpr_stack
; ASM32PWR4-NEXT: nop
; ASM32PWR4-NEXT: addi 1, 1, 144
; ASM32PWR4-NEXT: addi 1, 1, 160
; ASM32PWR4-NEXT: lwz 0, 8(1)
; ASM32PWR4-NEXT: mtlr 0
; ASM32PWR4-NEXT: blr
Expand All @@ -1667,7 +1679,6 @@ define void @caller_fpr_stack() {
; ASM64PWR4-NEXT: lis 7, 16313
; ASM64PWR4-NEXT: lwz 3, 0(3)
; ASM64PWR4-NEXT: ld 4, 0(4)
; ASM64PWR4-NEXT: lwz 5, 0(5)
; ASM64PWR4-NEXT: stw 3, 152(1)
; ASM64PWR4-NEXT: ld 3, L..C22(2) # %const.0
; ASM64PWR4-NEXT: std 4, 160(1)
Expand All @@ -1686,6 +1697,7 @@ define void @caller_fpr_stack() {
; ASM64PWR4-NEXT: ld 4, L..C29(2) # %const.7
; ASM64PWR4-NEXT: lfd 9, 0(3)
; ASM64PWR4-NEXT: ld 3, L..C30(2) # %const.8
; ASM64PWR4-NEXT: lwz 5, 0(5)
; ASM64PWR4-NEXT: lfd 1, 0(4)
; ASM64PWR4-NEXT: lis 4, 16320
; ASM64PWR4-NEXT: ori 4, 4, 41943
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/PowerPC/aix-cc-byval-mir.ll
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Expand Up @@ -134,7 +134,7 @@ define void @call_test_byval_3Byte() {
; 32BIT-NEXT: ADJCALLSTACKDOWN 60, 0, implicit-def dead $r1, implicit $r1
; 32BIT-NEXT: renamable $r3 = LI 42
; 32BIT-NEXT: renamable $r4 = LWZtoc @gS3, $r2 :: (load (s32) from got)
; 32BIT-NEXT: STW killed renamable $r3, 56, $r1 :: (store (s32))
; 32BIT-NEXT: STW killed renamable $r3, 56, $r1 :: (store (s32) into stack + 56, align 8, basealign 16)
; 32BIT-NEXT: renamable $r3 = LBZ 2, renamable $r4 :: (load (s8))
; 32BIT-NEXT: renamable $r4 = LHZ 0, killed renamable $r4 :: (load (s16))
; 32BIT-NEXT: renamable $r10 = RLWINM killed renamable $r3, 8, 16, 23
Expand All @@ -155,7 +155,7 @@ define void @call_test_byval_3Byte() {
; 64BIT-NEXT: ADJCALLSTACKDOWN 120, 0, implicit-def dead $r1, implicit $r1
; 64BIT-NEXT: renamable $x3 = LI8 42
; 64BIT-NEXT: renamable $x4 = LDtoc @gS3, $x2 :: (load (s64) from got)
; 64BIT-NEXT: STD killed renamable $x3, 112, $x1 :: (store (s64))
; 64BIT-NEXT: STD killed renamable $x3, 112, $x1 :: (store (s64) into stack + 112, align 16)
; 64BIT-NEXT: renamable $x3 = LBZ8 2, renamable $x4 :: (load (s8))
; 64BIT-NEXT: renamable $x4 = LHZ8 0, killed renamable $x4 :: (load (s16))
; 64BIT-NEXT: renamable $x10 = RLDIC killed renamable $x3, 40, 16
Expand Down
34 changes: 17 additions & 17 deletions llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
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Expand Up @@ -34,17 +34,17 @@ define double @caller() {
; MIR32-NEXT: STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r3 = LI 104
; MIR32-NEXT: STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r4 = LI 88
; MIR32-NEXT: STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
; MIR32-NEXT: STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r3 = LI 72
; MIR32-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got)
; MIR32-NEXT: STXVW4X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r3 = LI 88
; MIR32-NEXT: renamable $r4 = LI 72
; MIR32-NEXT: STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r3 = LI 48
; MIR32-NEXT: renamable $vsl0 = LXVD2X $zero, killed renamable $r4 :: (load (s128) from constant-pool)
; MIR32-NEXT: STXVW4X killed renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
; MIR32-NEXT: renamable $r4 = LI 512
; MIR32-NEXT: STXVD2X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128))
; MIR32-NEXT: STW killed renamable $r4, 152, $r1 :: (store (s32))
; MIR32-NEXT: STW killed renamable $r4, 152, $r1 :: (store (s32) into stack + 152, align 8, basealign 16)
; MIR32-NEXT: renamable $r4 = LWZtoc %const.0, $r2 :: (load (s32) from got)
; MIR32-NEXT: renamable $vsl0 = LXVD2X $zero, killed renamable $r4 :: (load (s128) from constant-pool)
; MIR32-NEXT: STXVD2X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128) into stack + 48)
; MIR32-NEXT: $f1 = XXLXORdpz
; MIR32-NEXT: $f2 = XXLXORdpz
; MIR32-NEXT: $v2 = XXLXORz
Expand Down Expand Up @@ -92,18 +92,18 @@ define double @caller() {
; MIR64-NEXT: ADJCALLSTACKDOWN 224, 0, implicit-def dead $r1, implicit $r1
; MIR64-NEXT: renamable $vsl0 = XXLXORz
; MIR64-NEXT: renamable $x3 = LI8 160
; MIR64-NEXT: STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
; MIR64-NEXT: STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128))
; MIR64-NEXT: renamable $x3 = LI8 144
; MIR64-NEXT: STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
; MIR64-NEXT: STXVW4X renamable $vsl0, $x1, killed renamable $x3 :: (store (s128))
; MIR64-NEXT: renamable $x3 = LI8 128
; MIR64-NEXT: STXVW4X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128), align 8)
; MIR64-NEXT: renamable $x3 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
; MIR64-NEXT: renamable $vsl0 = LXVD2X $zero8, killed renamable $x3 :: (load (s128) from constant-pool)
; MIR64-NEXT: renamable $x3 = LI8 80
; MIR64-NEXT: STXVD2X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128))
; MIR64-NEXT: STXVW4X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128))
; MIR64-NEXT: renamable $x3 = LI8 512
; MIR64-NEXT: STD killed renamable $x3, 184, $x1 :: (store (s64))
; MIR64-NEXT: STD killed renamable $x4, 176, $x1 :: (store (s64))
; MIR64-NEXT: STD killed renamable $x3, 184, $x1 :: (store (s64) into stack + 184, basealign 16)
; MIR64-NEXT: renamable $x3 = LI8 80
; MIR64-NEXT: STD killed renamable $x4, 176, $x1 :: (store (s64) into stack + 176, align 16)
; MIR64-NEXT: renamable $x4 = LDtocCPT %const.0, $x2 :: (load (s64) from got)
; MIR64-NEXT: renamable $vsl0 = LXVD2X $zero8, killed renamable $x4 :: (load (s128) from constant-pool)
; MIR64-NEXT: STXVD2X killed renamable $vsl0, $x1, killed renamable $x3 :: (store (s128) into stack + 80)
; MIR64-NEXT: $f1 = XXLXORdpz
; MIR64-NEXT: $f2 = XXLXORdpz
; MIR64-NEXT: $v2 = XXLXORz
Expand Down
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