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[MLIR][NVVM-Docs] Fix rendering of a few tables in NVVM Docs #144764

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Merged
merged 1 commit into from
Jun 19, 2025
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[MLIR][NVVM-Docs] Fix rendering of a few tables in NVVM Docs #144764

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10 changes: 8 additions & 2 deletions mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -3455,6 +3455,7 @@ def NVVM_Tcgen05MmaSmemDescOp : NVVM_Op<"tcgen05.mma_smem_desc", []> {
properties of multiplicand matrix in shared memory including its location
in the shared memory of the current CTA.

```
+-----------+------+------------------------------------------------------+
| Bit-field | Size | Description |
+-----------+------+------------------------------------------------------+
Expand All @@ -3477,6 +3478,7 @@ def NVVM_Tcgen05MmaSmemDescOp : NVVM_Op<"tcgen05.mma_smem_desc", []> {
| | | 6: 32-Byte swizzling |
| | | (Values 3, 5 and 7 are invalid) |
+-----------+------+------------------------------------------------------+
```

Example:
```mlir
Expand Down Expand Up @@ -3578,7 +3580,8 @@ def NVVM_Tcgen05LdOp : NVVM_Op<"tcgen05.ld", [NVVMRequiresSMa<[100, 101]>]> {
elements from adjacent columns into a single 32-bit element during the load.

The following table describes the size of the vector for various combinations
of `num` and `shape` attributes
of `num` and `shape` attributes:
```
|=====================================================================|
| num/shape | 16x32bx2/16x64b/32x32b | 16x128b | 16x256b |
|=====================================================================|
Expand All @@ -3591,6 +3594,7 @@ def NVVM_Tcgen05LdOp : NVVM_Op<"tcgen05.ld", [NVVMRequiresSMa<[100, 101]>]> {
| x64 | 64 | 128 | NA |
| x128 | 128 | NA | NA |
|=====================================================================|
```

Example:
```mlir
Expand Down Expand Up @@ -3666,7 +3670,8 @@ def NVVM_Tcgen05StOp : NVVM_Op<"tcgen05.st", [NVVMRequiresSMa<[100, 101]>]> {
in the register into two 16-bit elements and store them in adjacent columns.

The following table describes the size of the vector for various combinations
of `num` and `shape` attributes
of `num` and `shape` attributes:
```
|=====================================================================|
| num/shape | 16x32bx2/16x64b/32x32b | 16x128b | 16x256b |
|=====================================================================|
Expand All @@ -3679,6 +3684,7 @@ def NVVM_Tcgen05StOp : NVVM_Op<"tcgen05.st", [NVVMRequiresSMa<[100, 101]>]> {
| x64 | 64 | 128 | NA |
| x128 | 128 | NA | NA |
|=====================================================================|
```

Example:
```mlir
Expand Down
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