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[LLVM][AArch64] Relax SVE/SME codegen predicates. #145322

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Jul 2, 2025
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[LLVM][AArch64] Relax SVE/SME codegen predicates. #145322

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8 changes: 4 additions & 4 deletions llvm/lib/Target/AArch64/AArch64.td
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Original file line number Diff line number Diff line change
Expand Up @@ -58,11 +58,11 @@ include "AArch64SystemOperands.td"

class AArch64Unsupported { list<Predicate> F; }

let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_SME2p1] in
let F = [HasSVE2p1, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
def SVE2p1Unsupported : AArch64Unsupported;

def SVE2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVE2SM4, HasSVEBitPerm,
HasSVEB16B16],
SVE2p1Unsupported.F);
Expand All @@ -85,9 +85,9 @@ def SME2p1Unsupported : AArch64Unsupported {
}

def SME2Unsupported : AArch64Unsupported {
let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
HasNonStreamingSVE_or_SSVE_AES],
HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2],
SME2p1Unsupported.F);
}

Expand Down
22 changes: 14 additions & 8 deletions llvm/lib/Target/AArch64/AArch64InstrInfo.td
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Expand Up @@ -254,7 +254,7 @@ def HasNonStreamingSVE_or_SME2p1
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p1),
"sve or sme2p1">;
def HasNonStreamingSVE_or_SME2p2
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
: Predicate<"Subtarget->isSVEAvailable() ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2),
"sve or sme2p2">;
Expand All @@ -269,32 +269,38 @@ def HasNonStreamingSVE_or_SSVE_BitPerm
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm),
"sve or ssve-bitperm">;
def HasNonStreamingSVE_or_SSVE_FEXPA
: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||"
: Predicate<"Subtarget->isSVEAvailable() ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">,
AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_FEXPA),
"sve or ssve-fexpa">;

def HasSVE2_or_SME
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2() || Subtarget->hasSME())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME),
"sve2 or sme">;
def HasSVE2_or_SME2
: Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
def HasNonStreamingSVE2_or_SME2
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nit: maybe move these above HasSVE2_or_SME to bundle them together with the other HasNonStreamingSVE*_or_SME* ?

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I've tried to order the combined predicates based on the required SVE feature so that, for example, all SVE2 features are kept together.

: Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||"
"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2),
"sve2 or sme2">;

def HasSVE2p1_or_SME
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">,
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME())">,
AssemblerPredicateWithAll<(any_of FeatureSME, FeatureSVE2p1),
"sme or sve2p1">;
def HasSVE2p1_or_SME2
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2())">,
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),
"sme2 or sve2p1">;
def HasSVE2p1_or_SME2p1
: Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME2p1())">,
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p1() || Subtarget->hasSME2p1())">,
AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1),
"sme2p1 or sve2p1">;
def HasSVE2p1_or_StreamingSME2
: Predicate<"(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVE2p1()) ||"
"(Subtarget->isStreaming() && Subtarget->hasSME2())">,
AssemblerPredicateWithAll<(any_of FeatureSME2, FeatureSVE2p1),
"sme2 or sve2p1">;

def HasSVE2p2_or_SME2p2
: Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && (Subtarget->hasSVE2p2() || Subtarget->hasSME2p2())">,
Expand Down
43 changes: 23 additions & 20 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -4183,18 +4183,29 @@ defm UDOT_ZZZ_HtoS : sve2p1_two_way_dot_vv<"udot", 0b1, int_aarch64_sve_udot_x2
defm SDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"sdot", 0b0, int_aarch64_sve_sdot_lane_x2>;
defm UDOT_ZZZI_HtoS : sve2p1_two_way_dot_vvi<"udot", 0b1, int_aarch64_sve_udot_lane_x2>;

defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext", int_aarch64_sve_pext>;
defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;

defm SQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtn", 0b00, int_aarch64_sve_sqcvtn_x2>;
defm UQCVTN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"uqcvtn", 0b01, int_aarch64_sve_uqcvtn_x2>;
defm SQCVTUN_Z2Z_StoH : sve2p1_multi_vec_extract_narrow<"sqcvtun", 0b10, int_aarch64_sve_sqcvtun_x2>;
defm SQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrn", 0b101, int_aarch64_sve_sqrshrn_x2>;
defm UQRSHRN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"uqrshrn", 0b111, int_aarch64_sve_uqrshrn_x2>;
defm SQRSHRUN_Z2ZI_StoH : sve2p1_multi_vec_shift_narrow<"sqrshrun", 0b001, int_aarch64_sve_sqrshrun_x2>;

defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
} // End HasSVE2p1_or_SME2

let Predicates = [HasSVE2p1_or_StreamingSME2] in {
defm CNTP_XCI : sve2p1_pcount_pn<"cntp", 0b000>;
defm PEXT_PCI : sve2p1_pred_as_ctr_to_mask<"pext", int_aarch64_sve_pext>;
defm PEXT_2PCI : sve2p1_pred_as_ctr_to_mask_pair<"pext">;
defm PTRUE_C : sve2p1_ptrue_pn<"ptrue">;

// Load to two registers
defm LD1B_2Z : sve2p1_mem_cld_ss_2z<"ld1b", 0b00, 0b0, ZZ_b_mul_r, GPR64shifted8, ZZ_b_strided_and_contiguous>;
defm LD1H_2Z : sve2p1_mem_cld_ss_2z<"ld1h", 0b01, 0b0, ZZ_h_mul_r, GPR64shifted16, ZZ_h_strided_and_contiguous>;
Expand Down Expand Up @@ -4318,14 +4329,6 @@ defm : store_pn_x4<nxv8bf16, int_aarch64_sve_stnt1_pn_x4, STNT1H_4Z_IMM>;
defm : store_pn_x4<nxv4f32, int_aarch64_sve_stnt1_pn_x4, STNT1W_4Z_IMM>;
defm : store_pn_x4<nxv2f64, int_aarch64_sve_stnt1_pn_x4, STNT1D_4Z_IMM>;

defm WHILEGE_2PXX : sve2p1_int_while_rr_pair<"whilege", 0b000>;
defm WHILEGT_2PXX : sve2p1_int_while_rr_pair<"whilegt", 0b001>;
defm WHILELT_2PXX : sve2p1_int_while_rr_pair<"whilelt", 0b010>;
defm WHILELE_2PXX : sve2p1_int_while_rr_pair<"whilele", 0b011>;
defm WHILEHS_2PXX : sve2p1_int_while_rr_pair<"whilehs", 0b100>;
defm WHILEHI_2PXX : sve2p1_int_while_rr_pair<"whilehi", 0b101>;
defm WHILELO_2PXX : sve2p1_int_while_rr_pair<"whilelo", 0b110>;
defm WHILELS_2PXX : sve2p1_int_while_rr_pair<"whilels", 0b111>;
defm WHILEGE_CXX : sve2p1_int_while_rr_pn<"whilege", 0b000>;
defm WHILEGT_CXX : sve2p1_int_while_rr_pn<"whilegt", 0b001>;
defm WHILELT_CXX : sve2p1_int_while_rr_pn<"whilelt", 0b010>;
Expand All @@ -4334,7 +4337,7 @@ defm WHILEHS_CXX : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
} // End HasSVE2p1_or_SME2
} // End HasSVE2p1_or_StreamingSME2

let Predicates = [HasSVE_or_SME] in {

Expand Down Expand Up @@ -4539,7 +4542,7 @@ let Predicates = [HasNonStreamingSVE2p2_or_SME2p2] in {
//===----------------------------------------------------------------------===//
// SVE2 FP8 instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasSVE2_or_SME2, HasFP8] in {
let Predicates = [HasNonStreamingSVE2_or_SME2, HasFP8] in {
// FP8 upconvert
defm F1CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b00, "f1cvt", nxv8f16, int_aarch64_sve_fp8_cvt1>;
defm F2CVT_ZZ : sve2_fp8_cvt_single<0b0, 0b01, "f2cvt", nxv8f16, int_aarch64_sve_fp8_cvt2>;
Expand All @@ -4556,15 +4559,15 @@ defm FCVTNB_Z2Z_StoB : sve2_fp8_down_cvt_single<0b01, "fcvtnb", ZZ_s_mul_r, nxv4
defm BFCVTN_Z2Z_HtoB : sve2_fp8_down_cvt_single<0b10, "bfcvtn", ZZ_h_mul_r, nxv8bf16, int_aarch64_sve_fp8_cvtn>;

defm FCVTNT_Z2Z_StoB : sve2_fp8_down_cvt_single_top<0b11, "fcvtnt", ZZ_s_mul_r, nxv4f32, int_aarch64_sve_fp8_cvtnt>;
} // End HasSVE2_or_SME2, HasFP8
} // End HasNonStreamingSVE2_or_SME2, HasFP8

let Predicates = [HasSVE2_or_SME2, HasFAMINMAX] in {
let Predicates = [HasNonStreamingSVE2_or_SME2, HasFAMINMAX] in {
defm FAMIN_ZPmZ : sve_fp_2op_p_zds<0b1111, "famin", "FAMIN_ZPZZ", int_aarch64_sve_famin, DestructiveBinaryComm>;
defm FAMAX_ZPmZ : sve_fp_2op_p_zds<0b1110, "famax", "FAMAX_ZPZZ", int_aarch64_sve_famax, DestructiveBinaryComm>;

defm FAMAX_ZPZZ : sve_fp_bin_pred_hfd<AArch64famax_p>;
defm FAMIN_ZPZZ : sve_fp_bin_pred_hfd<AArch64famin_p>;
} // End HasSVE2_or_SME2, HasFAMINMAX
} // End HasNonStreamingSVE2_or_SME2, HasFAMINMAX

let Predicates = [HasSSVE_FP8FMA] in {
// FP8 Widening Multiply-Add Long - Indexed Group
Expand Down Expand Up @@ -4608,14 +4611,14 @@ defm FDOT_ZZZI_BtoS : sve2_fp8_dot_indexed_s<"fdot", int_aarch64_sve_fp8_fdot_la
defm FDOT_ZZZ_BtoS : sve_fp8_dot<0b1, ZPR32, "fdot", nxv4f32, int_aarch64_sve_fp8_fdot>;
}

let Predicates = [HasSVE2_or_SME2, HasLUT] in {
let Predicates = [HasNonStreamingSVE2_or_SME2, HasLUT] in {
// LUTI2
defm LUTI2_ZZZI : sve2_luti2_vector_index<"luti2">;
// LUTI4
defm LUTI4_ZZZI : sve2_luti4_vector_index<"luti4">;
// LUTI4 (two contiguous registers)
defm LUTI4_Z2ZZI : sve2_luti4_vector_vg2_index<"luti4">;
} // End HasSVE2_or_SME2, HasLUT
} // End HasNonStreamingSVE2_or_SME2, HasLUT

//===----------------------------------------------------------------------===//
// Checked Pointer Arithmetic (FEAT_CPA)
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/fp8-sve-cvt-cvtlt.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s
; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s
; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s

target triple = "aarch64-linux"
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mattr=+sve2,+fp8 < %s | FileCheck %s
; RUN: llc -mattr=+sve,+sme2,+fp8 < %s | FileCheck %s
; RUN: llc -mattr=+sme2,+fp8 --force-streaming < %s | FileCheck %s

target triple = "aarch64-linux"
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/sve-intrinsics-fexpa.ll
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@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -force-streaming -mattr=+ssve-fexpa < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+ssve-fexpa -force-streaming < %s | FileCheck %s

define <vscale x 8 x half> @fexpa_h(<vscale x 8 x i16> %a) {
; CHECK-LABEL: fexpa_h:
Expand All @@ -27,4 +27,4 @@ define <vscale x 2 x double> @fexpa_d(<vscale x 2 x i1> %pg, <vscale x 2 x i64>
; CHECK-NEXT: ret
%out = call <vscale x 2 x double> @llvm.aarch64.sve.fexpa.x.nxv2f64(<vscale x 2 x i64> %a)
ret <vscale x 2 x double> %out
}
}
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

; ADDHNB
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-complex-dot.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-faminmax.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mattr=+sve,+sme2 < %s | FileCheck %s
; RUN: llc -mattr=+sme2 -force-streaming < %s | FileCheck %s

target triple = "aarch64-linux"
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
Expand Down
1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
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@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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4 changes: 3 additions & 1 deletion llvm/test/CodeGen/AArch64/sve2-intrinsics-luti.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve2,+lut,+bf16 | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve2,+lut | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sve,+sme2,+lut | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+sme2,+lut --force-streaming | FileCheck %s

define <vscale x 16 x i8> @test_luti2_lane_i8(<vscale x 16 x i8> %table, <vscale x 16 x i8> %indices){
; CHECK-LABEL: test_luti2_lane_i8:
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-psel.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,sme -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s

define <vscale x 16 x i1> @psel_b(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {
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2 changes: 2 additions & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-revd.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming -verify-machineinstrs < %s | FileCheck %s

define <vscale x 16 x i8> @test_revd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %b) {
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-pairwise-arith.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
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