[AArch64] Separate PNR into its own Register Class #65306
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@@ -51,6 +51,8 @@ let Namespace = "AArch64" in { | |
| def zasubd1 : SubRegIndex<256>; // (16 x 16)/8 bytes = 256 bits | ||
| def zasubq0 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits | ||
| def zasubq1 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits | ||
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| def psub : SubRegIndex<16>; | ||
| } | ||
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| let Namespace = "AArch64" in { | ||
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@@ -763,23 +765,43 @@ def GPR64x8 : RegisterOperand<GPR64x8Class, "printGPR64x8"> { | |
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| //===----- END: v8.7a accelerator extension register operands -------------===// | ||
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| // SVE predicate-as-counter registers | ||
| def PN0 : AArch64Reg<0, "pn0">, DwarfRegNum<[48]>; | ||
| def PN1 : AArch64Reg<1, "pn1">, DwarfRegNum<[49]>; | ||
| def PN2 : AArch64Reg<2, "pn2">, DwarfRegNum<[50]>; | ||
| def PN3 : AArch64Reg<3, "pn3">, DwarfRegNum<[51]>; | ||
| def PN4 : AArch64Reg<4, "pn4">, DwarfRegNum<[52]>; | ||
| def PN5 : AArch64Reg<5, "pn5">, DwarfRegNum<[53]>; | ||
| def PN6 : AArch64Reg<6, "pn6">, DwarfRegNum<[54]>; | ||
| def PN7 : AArch64Reg<7, "pn7">, DwarfRegNum<[55]>; | ||
| def PN8 : AArch64Reg<8, "pn8">, DwarfRegNum<[56]>; | ||
| def PN9 : AArch64Reg<9, "pn9">, DwarfRegNum<[57]>; | ||
| def PN10 : AArch64Reg<10, "pn10">, DwarfRegNum<[58]>; | ||
| def PN11 : AArch64Reg<11, "pn11">, DwarfRegNum<[59]>; | ||
| def PN12 : AArch64Reg<12, "pn12">, DwarfRegNum<[60]>; | ||
| def PN13 : AArch64Reg<13, "pn13">, DwarfRegNum<[61]>; | ||
| def PN14 : AArch64Reg<14, "pn14">, DwarfRegNum<[62]>; | ||
| def PN15 : AArch64Reg<15, "pn15">, DwarfRegNum<[63]>; | ||
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| // SVE predicate registers | ||
| let SubRegIndices = [psub] in { | ||
| def P0 : AArch64Reg<0, "p0", [PN0]>, DwarfRegAlias<PN0>; | ||
| def P1 : AArch64Reg<1, "p1", [PN1]>, DwarfRegAlias<PN1>; | ||
| def P2 : AArch64Reg<2, "p2", [PN2]>, DwarfRegAlias<PN2>; | ||
| def P3 : AArch64Reg<3, "p3", [PN3]>, DwarfRegAlias<PN3>; | ||
| def P4 : AArch64Reg<4, "p4", [PN4]>, DwarfRegAlias<PN4>; | ||
| def P5 : AArch64Reg<5, "p5", [PN5]>, DwarfRegAlias<PN5>; | ||
| def P6 : AArch64Reg<6, "p6", [PN6]>, DwarfRegAlias<PN6>; | ||
| def P7 : AArch64Reg<7, "p7", [PN7]>, DwarfRegAlias<PN7>; | ||
| def P8 : AArch64Reg<8, "p8", [PN8]>, DwarfRegAlias<PN8>; | ||
| def P9 : AArch64Reg<9, "p9", [PN9]>, DwarfRegAlias<PN9>; | ||
| def P10 : AArch64Reg<10, "p10", [PN10]>, DwarfRegAlias<PN10>; | ||
| def P11 : AArch64Reg<11, "p11", [PN11]>, DwarfRegAlias<PN11>; | ||
| def P12 : AArch64Reg<12, "p12", [PN12]>, DwarfRegAlias<PN12>; | ||
| def P13 : AArch64Reg<13, "p13", [PN13]>, DwarfRegAlias<PN13>; | ||
| def P14 : AArch64Reg<14, "p14", [PN14]>, DwarfRegAlias<PN14>; | ||
| def P15 : AArch64Reg<15, "p15", [PN15]>, DwarfRegAlias<PN15>; | ||
| } | ||
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| // SVE variable-size vector registers | ||
| let SubRegIndices = [zsub] in { | ||
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@@ -842,8 +864,6 @@ class SVERegOp <string Suffix, AsmOperandClass C, | |
| let ParserMatchClass = C; | ||
| } | ||
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| class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size, | ||
| RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {} | ||
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@@ -852,7 +872,7 @@ class ZPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size, | |
| // SVE predicate register classes. | ||
| class PPRClass<int firstreg, int lastreg> : RegisterClass< | ||
| "AArch64", | ||
| [ nxv16i1, nxv8i1, nxv4i1, nxv2i1, nxv1i1 ], 16, | ||
| (sequence "P%u", firstreg, lastreg)> { | ||
| let Size = 16; | ||
| } | ||
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@@ -870,69 +890,89 @@ class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass { | |
| let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateVector>"; | ||
| } | ||
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| def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>; | ||
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There was a problem hiding this comment. This comment is for line 921: Is this register class still used somewhere? I thought we added this for instructions that take predicate-as-counter registers (which are passed in pn8-pn15). There was a problem hiding this comment. Sort of, It was used in c52d950 because there was no alternative PNR class to use at the time. It's probably not very useful now, unless you still want to be able to constrain the upper end of normal predicate when writing asm? Maybe its useful with some of the SVE2p1/SME2 strided/contiguous load instructions There was a problem hiding this comment. Okay, if it's not used at the moment, please remove it from this patch. If it's needed in the future we can always add it later. There was a problem hiding this comment. Sorry, just ignore my comment above. The code is already in and used in |
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| def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>; | ||
| def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>; | ||
| def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>; | ||
| def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>; | ||
| def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b", 0>; | ||
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| class PPRRegOp <string Suffix, AsmOperandClass C, ElementSizeEnum Size, | ||
| RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {} | ||
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| def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>; | ||
| def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>; | ||
| def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>; | ||
| def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>; | ||
| def PPR64 : PPRRegOp<"d", PPRAsmOp64, ElementSizeD, PPR>; | ||
| def PPR3bAny : PPRRegOp<"", PPRAsmOp3bAny, ElementSizeNone, PPR_3b>; | ||
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| class PNRClass<int firstreg, int lastreg> : RegisterClass< | ||
| "AArch64", | ||
| [ aarch64svcount ], 16, | ||
| (sequence "PN%u", firstreg, lastreg)> { | ||
| let Size = 16; | ||
| } | ||
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| def PNR : PNRClass<0, 15>; | ||
| def PNR_p8to15 : PNRClass<8, 15>; | ||
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| // SVE predicate-as-counter operand | ||
| class PNRAsmOperand<string name, string RegClass, int Width>: AsmOperandClass { | ||
| let Name = "SVE" # name # "Reg"; | ||
| let PredicateMethod = "isSVEPredicateAsCounterRegOfWidth<" | ||
| # Width # ", " # "AArch64::" | ||
| # RegClass # "RegClassID>"; | ||
| let DiagnosticType = "InvalidSVE" # name # "Reg"; | ||
| let RenderMethod = "addRegOperands"; | ||
| let ParserMethod = "tryParseSVEPredicateVector<RegKind::SVEPredicateAsCounter>"; | ||
| } | ||
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| let RenderMethod = "addPNRasPPRRegOperands" in { | ||
| def PNRasPPROpAny : PNRAsmOperand<"PNRasPPRPredicateAny", "PNR", 0>; | ||
| def PNRasPPROp8 : PNRAsmOperand<"PNRasPPRPredicateB", "PNR", 8>; | ||
| } | ||
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| class PNRasPPRRegOp<string Suffix, AsmOperandClass C, ElementSizeEnum Size, | ||
| RegisterClass RC> : SVERegOp<Suffix, C, Size, RC> {} | ||
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| def PNRasPPRAny : PNRasPPRRegOp<"", PNRasPPROpAny, ElementSizeNone, PPR>; | ||
| def PNRasPPR8 : PNRasPPRRegOp<"b", PNRasPPROp8, ElementSizeB, PPR>; | ||
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| def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PNR", 0>; | ||
| def PNRAsmOp8 : PNRAsmOperand<"PNPredicateB", "PNR", 8>; | ||
| def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PNR", 16>; | ||
| def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PNR", 32>; | ||
| def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PNR", 64>; | ||
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| class PNRRegOp<string Suffix, AsmOperandClass C, int Size, RegisterClass RC> | ||
| : SVERegOp<Suffix, C, ElementSizeNone, RC> { | ||
| let PrintMethod = "printPredicateAsCounter<" # Size # ">"; | ||
| } | ||
| def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0, PNR>; | ||
| def PNR8 : PNRRegOp<"b", PNRAsmOp8, 8, PNR>; | ||
| def PNR16 : PNRRegOp<"h", PNRAsmOp16, 16, PNR>; | ||
| def PNR32 : PNRRegOp<"s", PNRAsmOp32, 32, PNR>; | ||
| def PNR64 : PNRRegOp<"d", PNRAsmOp64, 64, PNR>; | ||
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| def PNRAsmAny_p8to15 : PNRAsmOperand<"PNPredicateAny_p8to15", "PNR_p8to15", 0>; | ||
| def PNRAsmOp8_p8to15 : PNRAsmOperand<"PNPredicateB_p8to15", "PNR_p8to15", 8>; | ||
| def PNRAsmOp16_p8to15 : PNRAsmOperand<"PNPredicateH_p8to15", "PNR_p8to15", 16>; | ||
| def PNRAsmOp32_p8to15 : PNRAsmOperand<"PNPredicateS_p8to15", "PNR_p8to15", 32>; | ||
| def PNRAsmOp64_p8to15 : PNRAsmOperand<"PNPredicateD_p8to15", "PNR_p8to15", 64>; | ||
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| class PNRP8to15RegOp<string Suffix, AsmOperandClass C, int Width, RegisterClass RC> | ||
| : SVERegOp<Suffix, C, ElementSizeNone, RC> { | ||
| let PrintMethod = "printPredicateAsCounter<" # Width # ">"; | ||
| let EncoderMethod = "EncodePNR_p8to15"; | ||
| let DecoderMethod = "DecodePNR_p8to15RegisterClass"; | ||
| } | ||
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| def PNRAny_p8to15 : PNRP8to15RegOp<"", PNRAsmAny_p8to15, 0, PNR_p8to15>; | ||
| def PNR8_p8to15 : PNRP8to15RegOp<"b", PNRAsmOp8_p8to15, 8, PNR_p8to15>; | ||
| def PNR16_p8to15 : PNRP8to15RegOp<"h", PNRAsmOp16_p8to15, 16, PNR_p8to15>; | ||
| def PNR32_p8to15 : PNRP8to15RegOp<"s", PNRAsmOp32_p8to15, 32, PNR_p8to15>; | ||
| def PNR64_p8to15 : PNRP8to15RegOp<"d", PNRAsmOp64_p8to15, 64, PNR_p8to15>; | ||
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| let Namespace = "AArch64" in { | ||
| def psub0 : SubRegIndex<16, -1>; | ||
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Could you add some tests for these COPYs?
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Added llvm/test/CodeGen/AArch64/PPRtoPNRCopy.mir and llvm/test/CodeGen/AArch64/PNRtoPPRCopy.mir