Skip to content

[CodeGen] Allow mixed scalar type constraints for inline asm #65465

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Aug 29, 2024
Merged

[CodeGen] Allow mixed scalar type constraints for inline asm #65465

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
52e62c6
[CodeGen] Allow mixed scalar type constraints for inline asm
dfszabo May 21, 2024
7eb5309
Merge branch 'main' into main-inline-asm-fix-fp-int-move
arsenm Aug 29, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 5 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9558,9 +9558,11 @@ static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
TLI.getRegForInlineAsmConstraint(TRI, MatchingOpInfo.ConstraintCode,
MatchingOpInfo.ConstraintVT);
if ((OpInfo.ConstraintVT.isInteger() !=
MatchingOpInfo.ConstraintVT.isInteger()) ||
(MatchRC.second != InputRC.second)) {
const bool OutOpIsIntOrFP =
OpInfo.ConstraintVT.isInteger() || OpInfo.ConstraintVT.isFloatingPoint();
const bool InOpIsIntOrFP = MatchingOpInfo.ConstraintVT.isInteger() ||
MatchingOpInfo.ConstraintVT.isFloatingPoint();
if ((OutOpIsIntOrFP != InOpIsIntOrFP) || (MatchRC.second != InputRC.second)) {
// FIXME: error out in a more elegant fashion
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
Expand Down
7 changes: 5 additions & 2 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5856,8 +5856,11 @@ TargetLowering::ParseConstraints(const DataLayout &DL,
std::pair<unsigned, const TargetRegisterClass *> InputRC =
getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
Input.ConstraintVT);
if ((OpInfo.ConstraintVT.isInteger() !=
Input.ConstraintVT.isInteger()) ||
const bool OutOpIsIntOrFP = OpInfo.ConstraintVT.isInteger() ||
OpInfo.ConstraintVT.isFloatingPoint();
const bool InOpIsIntOrFP = Input.ConstraintVT.isInteger() ||
Input.ConstraintVT.isFloatingPoint();
if ((OutOpIsIntOrFP != InOpIsIntOrFP) ||
(MatchRC.second != InputRC.second)) {
report_fatal_error("Unsupported asm: input constraint"
" with a matching output constraint of"
Expand Down
61 changes: 61 additions & 0 deletions llvm/test/CodeGen/X86/inline-asm-int-to-fp.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr +avx < %s | FileCheck %s

; The C source used as a base for generating this test:.

; unsigned test(float f)
; {
; unsigned i;
; // Copies f into the output operand i
; asm volatile ("" : "=r" (i) : "0" (f));
; return i;
; }


Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Add some comments explaining what this is showing

define i32 @test_int_float(float %f) {
; CHECK-LABEL: test_int_float:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovd %xmm0, %eax
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: retq
entry:
%asm_call = call i32 asm sideeffect "", "=r,0,~{dirflag},~{fpsr},~{flags}"(float %f)
ret i32 %asm_call
}

define i32 @test_int_ptr(ptr %f) {
; CHECK-LABEL: test_int_ptr:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: retq
entry:
%asm_call = call i32 asm sideeffect "", "=r,0,~{dirflag},~{fpsr},~{flags}"(ptr %f)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Is it really allowed to have the mismatched sizes, pointer 64 with i32? Should that be an x86-only thing?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

What about double + i32? Or i16 + float?

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Ugh. GCC seems to accept whatever garbage you give it.

ret i32 %asm_call
}

define i64 @test_int_vec(<4 x i16> %v) {
; CHECK-LABEL: test_int_vec:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vmovq %xmm0, %rax
; CHECK-NEXT: retq
entry:
%asm_call = call i64 asm sideeffect "", "=v,0,~{dirflag},~{fpsr},~{flags}"(<4 x i16> %v)
ret i64 %asm_call
}

define <4 x i32> @test_int_vec_float_vec(<4 x float> %f) {
; CHECK-LABEL: test_int_vec_float_vec:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: retq
entry:
%asm_call = call <4 x i32> asm sideeffect "", "=v,0,~{dirflag},~{fpsr},~{flags}"(<4 x float> %f)
ret <4 x i32> %asm_call
}
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can you also try the same, except with a mixed pointer and int/float? Also some vector cases?

Loading