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[GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT #65830

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Merged
merged 1 commit into from
Sep 12, 2023
Merged

[GIsel][AArch64] Legalize <2 x i16> for G_INSERT_VECTOR_ELT #65830

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11 changes: 11 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2493,6 +2493,17 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
return Legalized;
}
case TargetOpcode::G_INSERT_VECTOR_ELT: {
if (TypeIdx == 0) {
Observer.changingInstr(MI);
const LLT WideEltTy = WideTy.getElementType();

widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
widenScalarSrc(MI, WideEltTy, 2, TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy, 0);
Observer.changedInstr(MI);
return Legalized;
}

if (TypeIdx == 1) {
Observer.changingInstr(MI);

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3 changes: 1 addition & 2 deletions llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
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Expand Up @@ -718,8 +718,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)

getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
.legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
.clampMinNumElements(0, s16, 4)
.clampMaxNumElements(0, s16, 8);
.widenVectorEltsToVectorMinSize(0, 64);

getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8},
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42 changes: 42 additions & 0 deletions llvm/test/CodeGen/AArch64/GlobalISel/insert-vector-elt-pr63826.ll
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@@ -0,0 +1,42 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -o - -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -o - -verify-machineinstrs -global-isel=0 | FileCheck %s --check-prefixes=CHECK

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios14.5.0"

define <2 x i16> @pr63826_v2s16(<2 x i16> %vec) {
; CHECK-LABEL: pr63826_v2s16:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: mov.s v0[0], w8
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%vec1 = insertelement <2 x i16> %vec, i16 1, i32 0
ret <2 x i16> %vec1
}

define <2 x i8> @pr63826_v2s8(<2 x i8> %vec) {
; CHECK-LABEL: pr63826_v2s8:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: mov.s v0[0], w8
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%vec1 = insertelement <2 x i8> %vec, i8 1, i32 0
ret <2 x i8> %vec1
}

define <4 x i8> @pr63826_v4s8(<4 x i8> %vec) {
; CHECK-LABEL: pr63826_v4s8:
; CHECK: ; %bb.0:
; CHECK-NEXT: ; kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov w8, #1 ; =0x1
; CHECK-NEXT: mov.h v0[0], w8
; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0
; CHECK-NEXT: ret
%vec1 = insertelement <4 x i8> %vec, i8 1, i32 0
ret <4 x i8> %vec1
}
81 changes: 65 additions & 16 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
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@@ -1,24 +1,73 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
---
name: pr63826
name: pr63826_v2s16
body: |
bb.0:
; CHECK-LABEL: name: pr63826
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $w0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s16), [[C1]](s32)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
; CHECK-NEXT: $w0 = COPY [[UV2]](<2 x s16>)
%0:_(<2 x s16>) = COPY $w0
%1:_(s16) = G_CONSTANT i16 1
%2:_(s32) = G_CONSTANT i32 42
%4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
$w0 = COPY %4(<2 x s16>)
liveins: $d0
; CHECK-LABEL: name: pr63826_v2s16
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<2 x s32>) = COPY $d0
%0:_(<2 x s16>) = G_TRUNC %1(<2 x s32>)
%4:_(s32) = G_CONSTANT i32 0
%3:_(s16) = G_CONSTANT i16 1
%2:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0, %3(s16), %4(s32)
%5:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
$d0 = COPY %5(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: pr63826_v2s8
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: pr63826_v2s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s32), [[C]](s32)
; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<2 x s32>) = COPY $d0
%0:_(<2 x s8>) = G_TRUNC %1(<2 x s32>)
%4:_(s32) = G_CONSTANT i32 0
%3:_(s8) = G_CONSTANT i8 1
%2:_(<2 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
%5:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>)
$d0 = COPY %5(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: pr63826_v4s8
body: |
bb.0:
liveins: $d0
; CHECK-LABEL: name: pr63826_v4s8
; CHECK: liveins: $d0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], [[C1]](s16), [[C]](s32)
; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%1:_(<4 x s16>) = COPY $d0
%0:_(<4 x s8>) = G_TRUNC %1(<4 x s16>)
%4:_(s32) = G_CONSTANT i32 0
%3:_(s8) = G_CONSTANT i8 1
%2:_(<4 x s8>) = G_INSERT_VECTOR_ELT %0, %3(s8), %4(s32)
%5:_(<4 x s16>) = G_ANYEXT %2(<4 x s8>)
$d0 = COPY %5(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: v8s8
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