[clang-format] Properly indent lines inside Verilog case structure #65861
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When a statement following a case label had to be broken into multiple
lines, the continuation parts were not indented correctly.
Old:
```Verilog
case (data)
16'd0:
result = // break here
10'b0111111111;
endcase
```
New:
```Verilog
case (data)
16'd0:
result = // break here
10'b0111111111;
endcase
```
Verilog case labels and the following statements are on the same
unwrapped line due to the difficulty of identifying them. So there was
a rule in `getNewLineColumn` to add a level of indentation to the part
following the case label. However, in case the line had to be broken
again, the code at the end of the function would see that the line was
already broken with the continuation part indented, so it would not
indent it more. Now `State.FirstIndent` is changed as well for the part
following the case label, so the logic for determining when to add a
continuation indentation works.
llvmbot
added
clang
|
@llvm/pr-subscribers-clang ChangesWhen a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly. Old: case (data)
16'd0:
result = // break here
10'b0111111111;
endcaseNew: case (data)
16'd0:
result = // break here
10'b0111111111;
endcaseVerilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in
|
|
@llvm/pr-subscribers-clang-format ChangesWhen a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly. Old: case (data)
16'd0:
result = // break here
10'b0111111111;
endcaseNew: case (data)
16'd0:
result = // break here
10'b0111111111;
endcaseVerilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in
|
owenca
approved these changes
Sep 9, 2023
Comment on lines
1603
to
1605
| // Verilog case labels are are on the same unwrapped lines as the statements | ||
| // that follow. TokenAnnotator identifies them and sets MustBreakBefore. | ||
| // Indentation is taken care of here. A case label can only have 1 statement |
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Typo: are are. Also, use single space after ..
HazardyKnusperkeks
approved these changes
Sep 10, 2023
mydeveloperday
approved these changes
Sep 14, 2023
ZijunZhaoCCK
pushed a commit
to ZijunZhaoCCK/llvm-project
that referenced
this pull request
Sep 19, 2023
…lvm#65861) When a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly. Old: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` New: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` Verilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in `getNewLineColumn` to add a level of indentation to the part following the case label. However, in case the line had to be broken again, the code at the end of the function would see that the line was already broken with the continuation part indented, so it would not indent it more. Now `State.FirstIndent` is changed as well for the part following the case label, so the logic for determining when to add a continuation indentation works.
zahiraam
pushed a commit
to tahonermann/llvm-project
that referenced
this pull request
Oct 24, 2023
…lvm#65861) When a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly. Old: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` New: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` Verilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in `getNewLineColumn` to add a level of indentation to the part following the case label. However, in case the line had to be broken again, the code at the end of the function would see that the line was already broken with the continuation part indented, so it would not indent it more. Now `State.FirstIndent` is changed as well for the part following the case label, so the logic for determining when to add a continuation indentation works.
zahiraam
pushed a commit
to tahonermann/llvm-project
that referenced
this pull request
Oct 24, 2023
…lvm#65861) When a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly. Old: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` New: ```Verilog case (data) 16'd0: result = // break here 10'b0111111111; endcase ``` Verilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in `getNewLineColumn` to add a level of indentation to the part following the case label. However, in case the line had to be broken again, the code at the end of the function would see that the line was already broken with the continuation part indented, so it would not indent it more. Now `State.FirstIndent` is changed as well for the part following the case label, so the logic for determining when to add a continuation indentation works.
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When a statement following a case label had to be broken into multiple lines, the continuation parts were not indented correctly.
Old:
New:
Verilog case labels and the following statements are on the same unwrapped line due to the difficulty of identifying them. So there was a rule in
getNewLineColumnto add a level of indentation to the part following the case label. However, in case the line had to be broken again, the code at the end of the function would see that the line was already broken with the continuation part indented, so it would not indent it more. NowState.FirstIndentis changed as well for the part following the case label, so the logic for determining when to add a continuation indentation works.