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[DAGCombiner][RISCV] Prefer to sext i32 non-negative values #65984

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Merged
merged 1 commit into from
Sep 12, 2023
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[DAGCombiner][RISCV] Prefer to sext i32 non-negative values #65984

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3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -13271,7 +13271,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
return V;

// fold (sext x) -> (zext x) if the sign bit is known zero.
if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
(!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0);

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13 changes: 12 additions & 1 deletion llvm/test/CodeGen/RISCV/aext-to-sext.ll
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@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I

; Make sure we don't generate an addi in the loop in
Expand Down Expand Up @@ -100,3 +100,14 @@ merge:
%d = zext i32 %b to i64
ret i64 %d
}

; We prefer to sign extend i32 non-negative values. The default behavior in
; DAGCombiner is zero extend. We have a target hook to override it.
define signext i32 @square(i32 signext %num) {
; RV64I-LABEL: square:
; RV64I: # %bb.0:
; RV64I-NEXT: mulw a0, a0, a0
; RV64I-NEXT: ret
%mul = mul nsw i32 %num, %num
ret i32 %mul
}