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[Flang][OpenMP] Add trivial conversion pattern for omp.ordered_region #66085

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Merged
merged 1 commit into from
Sep 18, 2023
Merged

[Flang][OpenMP] Add trivial conversion pattern for omp.ordered_region #66085

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33 changes: 33 additions & 0 deletions flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
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Original file line number Diff line number Diff line change
Expand Up @@ -657,6 +657,7 @@ func.func @_QPs(%arg0: !fir.ref<!fir.complex<4>> {fir.bindc_name = "x"}) {
}

// -----

// Test if llvm.alloca is properly inserted in the omp section

//CHECK: %[[CONST:.*]] = llvm.mlir.constant(1 : i64) : i64
Expand Down Expand Up @@ -693,3 +694,35 @@ fir.global internal @_QFEx target : i32 {
%0 = fir.zero_bits i32
fir.has_value %0 : i32
}

// -----

// Test if llvm.alloca is properly inserted in the omp ordered region

// CHECK: llvm.func @sub_
func.func @sub_() {
%c0 = arith.constant 0 : index
%c1 = arith.constant 1 : index
%0 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsubEi"}
// CHECK: omp.ordered_region
omp.ordered_region {
%1 = fir.convert %c1 : (index) -> i32
cf.br ^bb1(%1, %c1 : i32, index)
^bb1(%2: i32, %3: index): // 2 preds: ^bb0, ^bb2
%4 = arith.cmpi sgt, %3, %c0 : index
cf.cond_br %4, ^bb2, ^bb3
^bb2: // pred: ^bb1
fir.store %2 to %0 : !fir.ref<i32>
%5 = fir.load %0 : !fir.ref<i32>
// CHECK: llvm.add
%6 = arith.addi %5, %1 : i32
// CHECK: llvm.sub
%7 = arith.subi %3, %c1 : index
cf.br ^bb1(%6, %7 : i32, index)
^bb3: // pred: ^bb1
fir.store %2 to %0 : !fir.ref<i32>
// CHECK: omp.terminator
omp.terminator
}
return
}
9 changes: 5 additions & 4 deletions mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
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Expand Up @@ -199,10 +199,10 @@ void mlir::configureOpenMPToLLVMConversionLegality(
ConversionTarget &target, LLVMTypeConverter &typeConverter) {
target.addDynamicallyLegalOp<
mlir::omp::AtomicUpdateOp, mlir::omp::CriticalOp, mlir::omp::TargetOp,
mlir::omp::DataOp, mlir::omp::ParallelOp, mlir::omp::WsLoopOp,
mlir::omp::SimdLoopOp, mlir::omp::MasterOp, mlir::omp::SectionOp,
mlir::omp::SectionsOp, mlir::omp::SingleOp, mlir::omp::TaskGroupOp,
mlir::omp::TaskOp>([&](Operation *op) {
mlir::omp::DataOp, mlir::omp::OrderedRegionOp, mlir::omp::ParallelOp,
mlir::omp::WsLoopOp, mlir::omp::SimdLoopOp, mlir::omp::MasterOp,
mlir::omp::SectionOp, mlir::omp::SectionsOp, mlir::omp::SingleOp,
mlir::omp::TaskGroupOp, mlir::omp::TaskOp>([&](Operation *op) {
return typeConverter.isLegal(&op->getRegion(0)) &&
typeConverter.isLegal(op->getOperandTypes()) &&
typeConverter.isLegal(op->getResultTypes());
Expand Down Expand Up @@ -234,6 +234,7 @@ void mlir::populateOpenMPToLLVMConversionPatterns(LLVMTypeConverter &converter,
AtomicReadOpConversion, ReductionOpConversion,
ReductionDeclareOpConversion, RegionOpConversion<omp::CriticalOp>,
RegionOpConversion<omp::MasterOp>, ReductionOpConversion,
RegionOpConversion<omp::OrderedRegionOp>,
RegionOpConversion<omp::ParallelOp>, RegionOpConversion<omp::WsLoopOp>,
RegionOpConversion<omp::SectionsOp>, RegionOpConversion<omp::SectionOp>,
RegionOpConversion<omp::SimdLoopOp>, RegionOpConversion<omp::SingleOp>,
Expand Down
31 changes: 31 additions & 0 deletions mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir
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Expand Up @@ -384,3 +384,34 @@ llvm.func @_QQmain() {
llvm.func @_QFPdo_work(%arg0: !llvm.ptr<i32> {fir.bindc_name = "i"}) {
llvm.return
}

// -----

// CHECK-LABEL: @sub_
llvm.func @sub_() {
%0 = llvm.mlir.constant(0 : index) : i64
%1 = llvm.mlir.constant(1 : index) : i64
%2 = llvm.mlir.constant(1 : i64) : i64
%3 = llvm.alloca %2 x i32 {bindc_name = "i", in_type = i32, operandSegmentSizes = array<i32: 0, 0>, uniq_name = "_QFsubEi"} : (i64) -> !llvm.ptr<i32>
// CHECK: omp.ordered_region
omp.ordered_region {
%4 = llvm.trunc %1 : i64 to i32
llvm.br ^bb1(%4, %1 : i32, i64)
^bb1(%5: i32, %6: i64): // 2 preds: ^bb0, ^bb2
%7 = llvm.icmp "sgt" %6, %0 : i64
llvm.cond_br %7, ^bb2, ^bb3
^bb2: // pred: ^bb1
llvm.store %5, %3 : !llvm.ptr<i32>
%8 = llvm.load %3 : !llvm.ptr<i32>
// CHECK: llvm.add
%9 = arith.addi %8, %4 : i32
// CHECK: llvm.sub
%10 = arith.subi %6, %1 : i64
llvm.br ^bb1(%9, %10 : i32, i64)
^bb3: // pred: ^bb1
llvm.store %5, %3 : !llvm.ptr<i32>
// CHECK: omp.terminator
omp.terminator
}
llvm.return
}