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[RISCV][NFC] Use !range bang operator #66494

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Merged
merged 3 commits into from
Oct 20, 2023
Merged

[RISCV][NFC] Use !range bang operator #66494

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d2cea80
[RISCV][NFC] Use !range bang operator
wangpc-pp Sep 15, 2023
33dec91
Replace 0-31 with !range to align others
wangpc-pp Sep 27, 2023
adb1320
Rewrite IndexSet
wangpc-pp Sep 27, 2023
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23 changes: 8 additions & 15 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -350,7 +350,7 @@ class NFList<int lmul> {
// Generate [start, end) SubRegIndex list.
class SubRegSet<int nf, int lmul> {
list<SubRegIndex> L = !foldl([]<SubRegIndex>,
[0, 1, 2, 3, 4, 5, 6, 7],
!range(0, 8),
AccList, i,
!listconcat(AccList,
!if(!lt(i, nf),
Expand Down Expand Up @@ -378,15 +378,9 @@ class IndexSet<int tuple_index, int nf, int lmul, bit isV0 = false> {
!foldl([]<int>,
!if(isV0, [0],
!cond(
!eq(lmul, 1):
[8, 9, 10, 11, 12, 13, 14, 15,
16, 17, 18, 19, 20, 21, 22, 23,
24, 25, 26, 27, 28, 29, 30, 31,
1, 2, 3, 4, 5, 6, 7],
!eq(lmul, 2):
[4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 1, 2, 3],
!eq(lmul, 4):
[2, 3, 4, 5, 6, 7, 1])),
!eq(lmul, 1): !listconcat(!range(8, 32), !range(1, 8)),
!eq(lmul, 2): !listconcat(!range(4, 16), !range(1, 4)),
!eq(lmul, 4): !listconcat(!range(2, 8), !range(1, 2)))),
L, i,
!listconcat(L,
!if(!le(!mul(!add(i, tuple_index), lmul),
Expand Down Expand Up @@ -416,12 +410,11 @@ class VRegList<list<dag> LIn, int start, int nf, int lmul, bit isV0> {
}

// Vector registers
foreach Index = 0-31 in {
foreach Index = !range(0, 32, 1) in {
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Why is this better?

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@wangpc-pp wangpc-pp Sep 27, 2023 •
edited
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It's not better, just to align other foreachs below. It may be more uniformed from the style perspective.

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If you want to do this kind of rewriting, then there are still many similar codes in this file.

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Thanks! IndexSet is rewritten.

def V#Index : RISCVReg<Index, "v"#Index>, DwarfRegNum<[!add(Index, 96)]>;
}

foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
24, 26, 28, 30] in {
foreach Index = !range(0, 32, 2) in {
def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index),
!cast<Register>("V"#!add(Index, 1))]>,
Expand All @@ -430,7 +423,7 @@ foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
}
}

foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
foreach Index = !range(0, 32, 4) in {
def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M2"),
!cast<Register>("V"#!add(Index, 2)#"M2")]>,
Expand All @@ -439,7 +432,7 @@ foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
}
}

foreach Index = [0, 8, 16, 24] in {
foreach Index = !range(0, 32, 8) in {
def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
[!cast<Register>("V"#Index#"M4"),
!cast<Register>("V"#!add(Index, 4)#"M4")]>,
Expand Down