[RISCV] Support floating point VCIX

[4vtomat]

No description provided.

[kito-cheng]

The target is support LLVM IR part only, we would like to prevent expose that on the C intrinsic level if possible, because that's intentionally to expose vector with unsigned integer only.

[4vtomat]

The target is support LLVM IR part only, we would like to prevent expose that on the C intrinsic level if possible, because that's intentionally to expose vector with unsigned integer only.

Sure~

[kito-cheng]

LGTM

[topperc]

Do we really need to support integer scalars with FP vectors?

[kito-cheng]

It's VCIX which could let user define what they want...which means it's also possible to design some function take an integer with floating point vector value, so I would say it possible, and support that on the LLVM IR only is harmless and not costly.

[topperc]

This patch increased the size of the isel table by 33K or 1.5%.

VCIX could also have an instruction that takes an FP vector and returns an int vector or vice versa, but we don't support that. So what is our criteria for what we support?

[kito-cheng]

Oh, okay, I got your point, I am thinking does it possible to convert those intrinsic to integer variant during lowering instead of expanding those combination in td?

[4vtomat]

I think that's a good idea, we just convert all floating point vector to integer vector during lowering, that can reduce the effort to create all of iteration in td file and also it could increase much size of isel table.