[PowerPC] Implement llvm.set.rounding intrinsic #67302
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According to LangRef, llvm.set.rounding sets rounding mode by integer argument:
0 - toward zero
1 - to nearest, ties to even
2 - toward positive infinity
3 - toward negative infinity
4 - to nearest, ties away from zero
While PowerPC ISA says:
0 - to nearest
1 - toward zero
2 - toward positive infinity
3 - toward negative infinity
This patch maps the argument and write into last two bits of FPSCR (rounding mode).
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The patch looks good but I am not familiar with PPC instructions enough. Could you please run the runtime tests from here: https://github.com/llvm/llvm-test-suite/tree/main/MultiSource/UnitTests/Float/rounding? You just need to build application from two files: clang rounding.c rounding-dynamic.c.
Sure. All passed on |
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LGTM. |
| SDValue Chain = Op.getOperand(0); | ||
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| // If requested mode is constant, just use simpler mtfsb. | ||
| if (auto *CVal = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { |
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Can we use DAG.computeKnownBits() to handle more cases instead of just the constant inputs?
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Here we want to make sure higher bits are all zeroes. KnownBits and constant don't make an difference?
| return SDValue(SetLo, 0); | ||
| } | ||
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| // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format. |
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The comment does not match below logic. x should be (x & 3)?
And the LLVM mode 4(4 - to nearest, ties away from zero) is mapped to Power mode 1(1 - toward zero)? I think LLVM mode 4 should map to Power mode 0(0- Round to Nearest)?
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I think we are using a at-best-effort approach. The meaning looks implementation-defined:
The
llvm.set.roundingintrinsic sets the current rounding mode. It is similar to C library function ‘fesetround’, however this intrinsic does not return any value and uses platform-independent representation of IEEE rounding modes.
| // Use x ^ (~(x >> 1) & 1) to transform LLVM rounding mode to Power format. | ||
| SDValue One = DAG.getConstant(1, Dl, MVT::i32); | ||
| SDValue SrcFlag = DAG.getNode(ISD::AND, Dl, MVT::i32, Op.getOperand(1), | ||
| DAG.getConstant(3, Dl, MVT::i32)); |
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Can we add an assert here too if compiler can infer that the high 29 bits of operand 1 is non-zero?
They are faster than system |
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Ping |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/5247 Here is the relevant piece of the build log for the reference |
According to LangRef, llvm.set.rounding sets rounding mode by integer argument:
While PowerPC ISA says:
This patch maps the argument and write into last two bits of FPSCR (rounding mode).
Migrated from https://reviews.llvm.org/D154933