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[AArch64] Fixes for BigEndian 128bit volatile, atomic and non-temporal loads/stores #67413

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[AArch64] Fixes for BigEndian 128bit volatile, atomic and non-temporal loads/stores #67413

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19 changes: 12 additions & 7 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5705,11 +5705,11 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
// legalization will break up 256 bit inputs.
ElementCount EC = MemVT.getVectorElementCount();
if (StoreNode->isNonTemporal() && MemVT.getSizeInBits() == 256u &&
EC.isKnownEven() &&
((MemVT.getScalarSizeInBits() == 8u ||
MemVT.getScalarSizeInBits() == 16u ||
MemVT.getScalarSizeInBits() == 32u ||
MemVT.getScalarSizeInBits() == 64u))) {
EC.isKnownEven() && DAG.getDataLayout().isLittleEndian() &&
(MemVT.getScalarSizeInBits() == 8u ||
MemVT.getScalarSizeInBits() == 16u ||
MemVT.getScalarSizeInBits() == 32u ||
MemVT.getScalarSizeInBits() == 64u)) {
SDValue Lo =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl,
MemVT.getHalfNumVectorElementsVT(*DAG.getContext()),
Expand Down Expand Up @@ -5769,6 +5769,8 @@ SDValue AArch64TargetLowering::LowerStore128(SDValue Op,
SDLoc DL(Op);
auto StoreValue = DAG.SplitScalar(Value, DL, MVT::i64, MVT::i64);
unsigned Opcode = IsStoreRelease ? AArch64ISD::STILP : AArch64ISD::STP;
if (DAG.getDataLayout().isBigEndian())
std::swap(StoreValue.first, StoreValue.second);
SDValue Result = DAG.getMemIntrinsicNode(
Opcode, DL, DAG.getVTList(MVT::Other),
{StoreNode->getChain(), StoreValue.first, StoreValue.second,
Expand Down Expand Up @@ -24169,8 +24171,11 @@ void AArch64TargetLowering::ReplaceNodeResults(
{LoadNode->getChain(), LoadNode->getBasePtr()},
LoadNode->getMemoryVT(), LoadNode->getMemOperand());

SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
Result.getValue(0), Result.getValue(1));
unsigned FirstRes = DAG.getDataLayout().isBigEndian() ? 1 : 0;

SDValue Pair =
DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128,
Result.getValue(FirstRes), Result.getValue(1 - FirstRes));
Results.append({Pair, Result.getValue(2) /* Chain */});
}
return;
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -229,59 +229,59 @@ define dso_local i64 @load_atomic_i64_aligned_seq_cst_const(ptr readonly %ptr) {

define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ishld
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ishld
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-lse2_lse128.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -229,59 +229,59 @@ define dso_local i64 @load_atomic_i64_aligned_seq_cst_const(ptr readonly %ptr) {

define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ishld
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ishld
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-load-rcpc3.ll
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Expand Up @@ -229,57 +229,57 @@ define dso_local i64 @load_atomic_i64_aligned_seq_cst_const(ptr readonly %ptr) {

define dso_local i128 @load_atomic_i128_aligned_unordered(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_unordered_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_unordered_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr unordered, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_monotonic_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_monotonic_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
%r = load atomic i128, ptr %ptr monotonic, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire:
; CHECK: ldiapp x1, x0, [x0]
; CHECK: ldiapp x0, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_acquire_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_acquire_const:
; CHECK: ldiapp x1, x0, [x0]
; CHECK: ldiapp x0, x1, [x0]
%r = load atomic i128, ptr %ptr acquire, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst(ptr %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
}

define dso_local i128 @load_atomic_i128_aligned_seq_cst_const(ptr readonly %ptr) {
; CHECK-LABEL: load_atomic_i128_aligned_seq_cst_const:
; CHECK: ldp x1, x0, [x0]
; CHECK: ldp x0, x1, [x0]
; CHECK: dmb ish
%r = load atomic i128, ptr %ptr seq_cst, align 16
ret i128 %r
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-lse2.ll
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Expand Up @@ -117,30 +117,30 @@ define dso_local void @store_atomic_i64_aligned_seq_cst(i64 %value, ptr %ptr) {

define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_unordered:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr unordered, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_monotonic:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr monotonic, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_release:
; CHECK: dmb ish
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr release, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_seq_cst:
; CHECK: dmb ish
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
; CHECK: dmb ish
store atomic i128 %value, ptr %ptr seq_cst, align 16
ret void
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-lse2_lse128.ll
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Expand Up @@ -117,14 +117,14 @@ define dso_local void @store_atomic_i64_aligned_seq_cst(i64 %value, ptr %ptr) {

define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_unordered:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr unordered, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_monotonic:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr monotonic, align 16
ret void
}
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomic-store-rcpc3.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -117,29 +117,29 @@ define dso_local void @store_atomic_i64_aligned_seq_cst(i64 %value, ptr %ptr) {

define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_unordered:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr unordered, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_monotonic(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_monotonic:
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
store atomic i128 %value, ptr %ptr monotonic, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_release(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_release:
; CHECK: stilp x1, x0, [x2]
; CHECK: stilp x0, x1, [x2]
store atomic i128 %value, ptr %ptr release, align 16
ret void
}

define dso_local void @store_atomic_i128_aligned_seq_cst(i128 %value, ptr %ptr) {
; CHECK-LABEL: store_atomic_i128_aligned_seq_cst:
; CHECK: dmb ish
; CHECK: stp x1, x0, [x2]
; CHECK: stp x0, x1, [x2]
; CHECK: dmb ish
store atomic i128 %value, ptr %ptr seq_cst, align 16
ret void
Expand Down
29 changes: 11 additions & 18 deletions llvm/test/CodeGen/AArch64/i128_volatile_load_store.ll
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Expand Up @@ -129,15 +129,10 @@ entry:
}

define i128 @load_vol(i32, i32, ptr %p) {
; CHECK-LE-LABEL: load_vol:
; CHECK-LE: // %bb.0: // %entry
; CHECK-LE-NEXT: ldp x0, x1, [x2]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: load_vol:
; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: ldp x1, x0, [x2]
; CHECK-BE-NEXT: ret
; CHECK-LABEL: load_vol:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldp x0, x1, [x2]
; CHECK-NEXT: ret
entry:
%l = load volatile i128, ptr %p, align 16
ret i128 %l
Expand All @@ -154,16 +149,14 @@ entry:
}

define void @loadstore_vol(i128 %a, ptr %p) {
; CHECK-LE-LABEL: loadstore_vol:
; CHECK-LE: // %bb.0: // %entry
; CHECK-LE-NEXT: stp x0, x1, [x2]
; CHECK-LE-NEXT: ret
;
; CHECK-BE-LABEL: loadstore_vol:
; CHECK-BE: // %bb.0: // %entry
; CHECK-BE-NEXT: stp x1, x0, [x2]
; CHECK-BE-NEXT: ret
; CHECK-LABEL: loadstore_vol:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: stp x0, x1, [x2]
; CHECK-NEXT: ret
entry:
store volatile i128 %a, ptr %p, align 16
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-BE: {{.*}}
; CHECK-LE: {{.*}}
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