[GlobalISel] Combine (X == 0) & (Y == 0) -> (X | Y) == 0

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

@@ -805,6 +805,10 @@ class CombinerHelper {
   ///   (X ^ Y) != X -> Y != 0
   bool matchRedundantBinOpInEquality(MachineInstr &MI, BuildFnTy &MatchInfo);
 
+  /// Transform: (X == 0 & Y == 0) -> (X | Y) == 0
+  ///            (X != 0 | Y != 0) -> (X | Y) != 0
+  bool matchDoubleICmpZeroAndOr(MachineInstr &MI, BuildFnTy &MatchInfo);
+
   /// Match shifts greater or equal to the bitwidth of the operation.
   bool matchShiftsTooBig(MachineInstr &MI);
 

llvm/include/llvm/Target/GlobalISel/Combine.td

@@ -903,6 +903,12 @@ def redundant_binop_in_equality : GICombineRule<
          [{ return Helper.matchRedundantBinOpInEquality(*${root}, ${info}); }]),
   (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
 
+def double_icmp_zero_and_or_combine : GICombineRule<
+  (defs root:$root, build_fn_matchinfo:$info),
+  (match (wip_match_opcode G_AND, G_OR):$root,
+    [{ return Helper.matchDoubleICmpZeroAndOr(*${root}, ${info}); }]),
+  (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
+
 def and_or_disjoint_mask : GICombineRule<
   (defs root:$root, build_fn_matchinfo:$info),
   (match (wip_match_opcode G_AND):$root,
@@ -1265,7 +1271,7 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
     intdiv_combines, mulh_combines, redundant_neg_operands,
     and_or_disjoint_mask, fma_combines, fold_binop_into_select,
     sub_add_reg, select_to_minmax, redundant_binop_in_equality,
-    fsub_to_fneg, commute_constant_to_rhs]>;
+    double_icmp_zero_and_or_combine, fsub_to_fneg, commute_constant_to_rhs]>;
 
 // A combine group used to for prelegalizer combiners at -O0. The combines in
 // this group have been selected based on experiments to balance code size and

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

@@ -6066,6 +6066,47 @@ bool CombinerHelper::matchRedundantBinOpInEquality(MachineInstr &MI,
   return CmpInst::isEquality(Pred) && Y.isValid();
 }
 
+bool CombinerHelper::matchDoubleICmpZeroAndOr(
+    MachineInstr &MI, std::function<void(MachineIRBuilder &)> &MatchInfo) {
+  const unsigned Opcode = MI.getOpcode();
+  assert(Opcode == TargetOpcode::G_OR || Opcode == TargetOpcode::G_AND);
+
+  const Register Dst = MI.getOperand(0).getReg();
+  CmpInst::Predicate LHSPred, RHSPred;
+  int64_t LHSImm, RHSImm;
+  Register LHSCmpSrc, RHSCmpSrc;
+  if (!mi_match(
+          Dst, MRI,
+          m_BinOp(Opcode,
+                  m_GICmp(m_Pred(LHSPred), m_Reg(LHSCmpSrc), m_ICst(LHSImm)),
+                  m_GICmp(m_Pred(RHSPred), m_Reg(RHSCmpSrc), m_ICst(RHSImm)))))
+    return false;
+
+  // G_OR and G_AND cannot handle pointers
+  const auto LHSSrcTy = MRI.getType(LHSCmpSrc);
+  if (LHSSrcTy != MRI.getType(RHSCmpSrc) || LHSSrcTy.isPointer())
+    return false;
+
+  const bool IsAnd = Opcode == TargetOpcode::G_AND;
+  if ((IsAnd && LHSPred != CmpInst::ICMP_EQ) ||
+      (!IsAnd && LHSPred != CmpInst::ICMP_NE) || LHSPred != RHSPred)
+    return false;
+
+  if (LHSImm != 0 || RHSImm != 0)
+    return false;
+
+  MatchInfo = [=](MachineIRBuilder &B) {
+    const Register OrDst = MRI.createGenericVirtualRegister(LHSSrcTy);
+    auto Zero = B.buildConstant(LHSSrcTy, 0);
+    B.buildOr(OrDst, LHSCmpSrc, RHSCmpSrc);
+    B.buildICmp(IsAnd ? CmpInst::Predicate::ICMP_EQ
+                      : CmpInst::Predicate::ICMP_NE,
+                Dst, OrDst, Zero);
+  };
+
+  return true;
+}
+
 bool CombinerHelper::matchShiftsTooBig(MachineInstr &MI) {
   Register ShiftReg = MI.getOperand(2).getReg();
   LLT ResTy = MRI.getType(MI.getOperand(0).getReg());